[PATCH] D69578: [AIX] Add support for lowering int, float and double formal arguments.

Wed Oct 30 10:52:10 PDT 2019

sfertile added inline comments.
Herald added a subscriber: wuzish.

================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:6705
+  case MVT::i32:
+  case MVT::i64:
+    return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
----------------
My understanding is that when targeting 32-bit codegen any i64 will be split into 2 i32s. If thats correct then we should  keep the i64 case separate, with an assert along the lines of `assert(IsPPC64 && "i64 should have been split for 32-bit codegen.");`.

================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:6812
+    report_fatal_error("QPX support is not supported on AIX.");
+  if (Subtarget.hasAltivec())
+    report_fatal_error("Altivec support is unimplemented on AIX.");
----------------
I believe this is breaking some of the existing AIX lit testing.

================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:6841
+      if (ValVT == MVT::i1)
+        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
+      // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
----------------
Shouldn't we be doing the same thing `extendArgForPPC64` is doing, but with the extra generality that the zext/zext type should be i32 when targeting 32-bit codegen?

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69578/new/

https://reviews.llvm.org/D69578