[PATCH] D47192: [utils] Reflow asm check generation to tolerate blank lines

Wed Oct 30 10:17:11 PDT 2019

atanasyan updated this revision to Diff 227135.
atanasyan edited the summary of this revision.
atanasyan added a comment.
Herald added subscribers: jrtc27, arichardson.

- Emit CHECK-EMPTY prefix for an empty line in ASM output
- Add MIPS related fix and update test case to check the changes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D47192/new/

https://reviews.llvm.org/D47192

Files:
  llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
  llvm/utils/UpdateTestChecks/asm.py
  llvm/utils/UpdateTestChecks/common.py


Index: llvm/utils/UpdateTestChecks/common.py
===================================================================

--- llvm/utils/UpdateTestChecks/common.py
+++ llvm/utils/UpdateTestChecks/common.py
@@ -226,7 +226,10 @@
       if is_asm:
         output_lines.append('%s %s:       %s' % (comment_marker, checkprefix, func_body[0]))
         for func_line in func_body[1:]:
-          output_lines.append('%s %s-NEXT:  %s' % (comment_marker, checkprefix, func_line))
+          if func_line.strip() == '':
+            output_lines.append('%s %s-EMPTY:' % (comment_marker, checkprefix))
+          else:
+            output_lines.append('%s %s-NEXT:  %s' % (comment_marker, checkprefix, func_line))
         break
 
       # For IR output, change all defs to FileCheck variables, so we're immune
Index: llvm/utils/UpdateTestChecks/asm.py
===================================================================
--- llvm/utils/UpdateTestChecks/asm.py
+++ llvm/utils/UpdateTestChecks/asm.py
@@ -53,7 +53,8 @@
     r'^_?(?P<func>[^:]+):[ \t]*#+[ \t]*@(?P=func)\n[^:]*?' # f: (name of func)
     r'(?:^[ \t]+\.(frame|f?mask|set).*?\n)+'  # Mips+LLVM standard asm prologue
     r'(?P<body>.*?)\n'                        # (body of the function)
-    r'(?:^[ \t]+\.(set|end).*?\n)+'           # Mips+LLVM standard asm epilogue
+    # Mips+LLVM standard asm epilogue
+    r'(?:(^[ \t]+\.set[^\n]*?\n)*^[ \t]+\.end.*?\n)'
     r'(\$|\.L)func_end[0-9]+:\n',             # $func_end0: (mips32 - O32) or
                                               # .Lfunc_end0: (mips64 - NewABI)
     flags=(re.M | re.S))
Index: llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
===================================================================
--- llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
+++ llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;
 ; Register constraint "r" shouldn't take long long unless
 ; The target is 64 bit.
@@ -7,13 +8,25 @@
 
 
 define i32 @main() nounwind {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    daddiu $1, $zero, 7
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    .set push
+; CHECK-NEXT:    .set at
+; CHECK-NEXT:    .set macro
+; CHECK-NEXT:    .set reorder
+; CHECK-EMPTY:
+; CHECK-NEXT:    addiu $1, $1, 3
+; CHECK-EMPTY:
+; CHECK-NEXT:    .set pop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    addiu $2, $zero, 0
 entry:
 
 
 ; r with long long
-;CHECK:	#APP
-;CHECK:	addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
-;CHECK:	#NO_APP
   tail call i64 asm sideeffect "addiu $0, $1, $2", "=r,r,i"(i64 7, i64 3) nounwind
   ret i32 0
 }


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