[llvm] 14e289e - Fix pattern error for S2_tstbit_i instruction

[Brian Cain via llvm-commits]

Author: Ikhlas Ajbar
Date: 2019-10-30T11:21:48-05:00
New Revision: 14e289eb774ebbc2fc788bf23c17e2605c27ffb6

URL: https://github.com/llvm/llvm-project/commit/14e289eb774ebbc2fc788bf23c17e2605c27ffb6
DIFF: https://github.com/llvm/llvm-project/commit/14e289eb774ebbc2fc788bf23c17e2605c27ffb6.diff

LOG: Fix pattern error for S2_tstbit_i instruction

It used to generate S2_tstbit_i with constant -33 which resulted in an assert.
The reason is log2_32 was called with 64bit value 0.

Added: 
    llvm/test/CodeGen/Hexagon/64bit_tstbit.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonPatterns.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 485e658e1c84..cf711058823c 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -1817,9 +1817,9 @@ def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)),
 def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)),
          (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>;
 def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)),
-         (S2_tstbit_i (LoReg $Rs), (Log2_32 imm:$u6))>;
+         (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>;
 def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)),
-         (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_32 imm:$u6))))>;
+         (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>;
 
 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
 // represented as a compare against "value & 0xFF", which is an exact match

diff  --git a/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll b/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
new file mode 100644
index 000000000000..b265d1bef6fe
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
@@ -0,0 +1,34 @@
+; RUN: llc -march=hexagon  < %s | FileCheck %s
+
+; This test checks that S2_tstbit_i instruction is generated
+; and it does not assert.
+
+; CHECK: p{{[0-9]+}} = tstbit
+
+
+target triple = "hexagon-unknown-unknown-elf"
+
+%struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192 = type { %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192*, %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192** }
+
+ at .str.8 = external dso_local unnamed_addr constant [5 x i8], align 1
+
+declare dso_local void @panic(i8*, ...) local_unnamed_addr
+
+define dso_local fastcc void @elv_rqhash_find() unnamed_addr {
+entry:
+  %cmd_flags = getelementptr inbounds %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192, %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192* null, i32 -5
+  %0 = bitcast %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192* %cmd_flags to i64*
+  %1 = load i64, i64* %0, align 8
+  %2 = and i64 %1, 4294967296
+  %tobool10 = icmp eq i64 %2, 0
+  br i1 %tobool10, label %do.body11, label %do.end14
+
+do.body11:                                        ; preds = %entry
+  tail call void (i8*, ...) @panic(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.8, i32 0, i32 0)) #1
+  unreachable
+
+do.end14:                                         ; preds = %entry
+  %and.i = and i64 %1, -4294967297
+  store i64 %and.i, i64* %0, align 8
+  ret void
+}