[PATCH] D69614: Fix pattern error for S2_tstbit_i instruction
Brian Cain via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 30 06:05:13 PDT 2019
bcain created this revision.
bcain added reviewers: kparzysz, iajbar.
bcain added a project: LLVM.
Herald added a subscriber: hiraditya.
It used to generate S2_tstbit_i with constant -33 which resulted in an assert.
The reason is log2_32 was called with 64bit value 0.
Patch by Ikhlas Ajbar <iajbar at quicinc.com>
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D69614
Files:
llvm/lib/Target/Hexagon/HexagonPatterns.td
llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
Index: llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
@@ -0,0 +1,35 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; This test checks that S2_tstbit_i instruction is generated
+; and it does not assert.
+
+; CHECK: p{{[0-9]+}} = tstbit
+
+
+target triple = "hexagon-unknown-unknown-elf"
+
+%struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192 = type { %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192*, %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192** }
+
+ at .str.8 = external dso_local unnamed_addr constant [5 x i8], align 1
+
+declare dso_local void @panic(i8*, ...) local_unnamed_addr
+
+define dso_local fastcc void @elv_rqhash_find() unnamed_addr {
+entry:
+ %cmd_flags = getelementptr inbounds %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192, %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192* null, i32 -5
+ %0 = bitcast %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192* %cmd_flags to i64*
+ %1 = load i64, i64* %0, align 8
+ %2 = and i64 %1, 4294967296
+ %tobool10 = icmp eq i64 %2, 0
+ br i1 %tobool10, label %do.body11, label %do.end14
+
+do.body11: ; preds = %entry
+ tail call void (i8*, ...) @panic(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.8, i32 0, i32 0)) #1
+ unreachable
+
+do.end14: ; preds = %entry
+ %and.i = and i64 %1, -4294967297
+ store i64 %and.i, i64* %0, align 8
+ ret void
+}
+
Index: llvm/lib/Target/Hexagon/HexagonPatterns.td
===================================================================
--- llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -1867,9 +1867,9 @@
def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)),
(S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>;
def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)),
- (S2_tstbit_i (LoReg $Rs), (Log2_32 imm:$u6))>;
+ (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>;
def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)),
- (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_32 imm:$u6))))>;
+ (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>;
// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
// represented as a compare against "value & 0xFF", which is an exact match
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