[PATCH] D69584: [LDV][RAGreedy] Inform LiveDebugVariables about new VRegs added by InlineSpiller

Tue Oct 29 13:32:27 PDT 2019

bjope created this revision.
bjope added reviewers: jmorse, vsk, aprantl.
Herald added subscribers: jsji, hiraditya, nemanjai, qcolombet, MatzeB.
Herald added a project: LLVM.
Herald added a subscriber: wuzish.

Make sure RAGreedy informs LiveDebugVariables about new VRegs
that is introduced at spill by InlineSpiller.

Consider this example

LDV: !"var"	 [48r;128r):0 Loc0=%2

48B   %2 = ...
 ...
 128B  %7 = ADD %2, ...

If %2 is spilled the InlineSpiller will insert spill/reload
instructions and introduces some new vregs. So we get

48B   %4 = ...
 56B   spill %4
 ...
 120B  reload %5
 128B  %3 = ADD %5, ...

In the past we did not inform LDV about this, and when reintroducing
DBG_VALUE instruction LDV still got information that "var" had the
location of the spilled register %2 for the interval [48r;128r).
The result was bad, since we mapped "var" to the spill slot even
before the spill happened:

%4 = ...
 DBG_VALUE %spill.0, !"var"
 spill %4 to %spill.0
 ...
 reload %5
 %3 = ADD %5, ...

This patch will inform LDV about the interval split introduced
due to spilling. So the location map in LDV will become

!"var"	[48r;56r):1 [56r;120r):0 [120r;128r):2 Loc0=%2 Loc1=%4 Loc2=%5

And when inserting DBG_VALUE instructions we get

%4 = ...
 DBG_VALUE %4, !"var"
 spill %4 to %spill.0
 DBG_VALUE %spill.0, !"var"
 ...
 reload %5
 DBG_VALUE %5, !"var"
 %3 = ADD %5, ...

Fixes: https://bugs.llvm.org/show_bug.cgi?id=38899

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69584

Files:
  llvm/lib/CodeGen/LiveDebugVariables.cpp
  llvm/lib/CodeGen/RegAllocGreedy.cpp
  llvm/test/CodeGen/PowerPC/pr38899-split-register-at-spill.mir

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