[PATCH] D69551: [PowerPC] Fix the incorrect 'RM' flag set on load/store instr

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: nemanjai, hfinkel, jsji, PowerPC.
Herald added subscribers: shchenz, wuzish, kbarton, hiraditya.
Herald added a project: LLVM.

The 'RM' flag model the "Rounding Mode" and it has nothing to do with the load/store instructions.


https://reviews.llvm.org/D69551

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/instr-properties.ll


Index: llvm/test/CodeGen/PowerPC/instr-properties.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/instr-properties.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-misched -stop-after=machine-scheduler -o - | FileCheck %s --check-prefix=CHECK-P8
+
+; Verify XFLOADf64 didn't implict def 'rm'.
+define double @rm() {
+; CHECK-P8-LABEL: bb.0.entry
+; CHECK-P8: %{{[0-9]+}}:vsfrc = XFLOADf64 $zero8, %{{[0-9]+}} ::
+entry:
+  ret double 2.300000e+00
+}
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -152,7 +152,6 @@
 let Predicates = [HasVSX] in {
 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
 let hasSideEffects = 0 in { // VSX instructions don't have side effects.
-let Uses = [RM] in {
 
   // Load indexed instructions
   let mayLoad = 1, mayStore = 0 in {
@@ -214,6 +213,7 @@
     }
   } // mayStore
 
+  let Uses = [RM] in {
   // Add/Mul Instructions
   let isCommutable = 1 in {
     def XSADDDP : XX3Form<60, 32,


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