[PATCH] D69219: [SelectionDAG] Enable lowering unordered atomics loads w/LoadSDNode (and stores w/StoreSDNode) by default

[Philip Reames via Phabricator via llvm-commits]

reames updated this revision to Diff 226775.
reames added a comment.
This revision is now accepted and ready to land.

Add the missing type legalization, and asserts.  I had failed to account for the fact that we don't expand atomic loads/stores which aren't natively legal, but can be represented as cmpxchg in IR, despite having a mechanism to do so.

This version looks to correct the bug in the test cases spotted, but I'm still nervous.  There's code in LegalizeDAG.cpp (as opposed to type legalization) for ATOMIC_LOAD and ATOMIC_STORE which I don't have a parallel for, and which appears to be dead.  (I added assert(false) and no x86 tests failed.)  I don't really know what to do beyond that though.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69219/new/

https://reviews.llvm.org/D69219

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
  llvm/test/CodeGen/X86/atomic-non-integer.ll
  llvm/test/CodeGen/X86/atomic-unordered.ll
  llvm/test/CodeGen/X86/combineIncDecVector-crash.ll

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