[llvm] 0f6ed43 - [AArch64][GlobalISel] Fix assertion fail in C++ selection for vector zext of <4 x s8>

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2019-10-28T15:45:01-07:00
New Revision: 0f6ed432d58e47e7082bfd44d7b29f3ee54e2642

URL: https://github.com/llvm/llvm-project/commit/0f6ed432d58e47e7082bfd44d7b29f3ee54e2642
DIFF: https://github.com/llvm/llvm-project/commit/0f6ed432d58e47e7082bfd44d7b29f3ee54e2642.diff

LOG: [AArch64][GlobalISel] Fix assertion fail in C++ selection for vector zext of <4 x s8>

We bailed out of dealing with vectors only after the assertion, move it before.

Fixes PR43794

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 961f38cad1e4..c9d4654ade05 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -2065,14 +2065,15 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
     unsigned DstSize = DstTy.getSizeInBits();
     unsigned SrcSize = SrcTy.getSizeInBits();
 
+    if (DstTy.isVector())
+      return false; // Should be handled by imported patterns.
+
     assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() ==
                AArch64::GPRRegBankID &&
            "Unexpected ext regbank");
 
     MachineIRBuilder MIB(I);
     MachineInstr *ExtI;
-    if (DstTy.isVector())
-      return false; // Should be handled by imported patterns.
 
     // First check if we're extending the result of a load which has a dest type
     // smaller than 32 bits, then this zext is redundant. GPR32 is the smallest

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index cd247718eba0..dab44b84355e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -200,3 +200,12 @@ entry:
   call void @use_s128(i128 %p2, i128 %p6)
   ret i32 0
 }
+
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: %2:fpr(<4 x s16>) = G_ZEXT %0:fpr(<4 x s8>) (in function: zext_v4s8)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for zext_v4s8
+; FALLBACK-WITH-REPORT-OUT-LABEL: zext_v4s8
+define <4 x i16> @zext_v4s8(<4 x i8> %in) {
+  %ext = zext <4 x i8> %in to <4 x i16>
+  ret <4 x i16> %ext
+}
+