[PATCH] D69390: [RISCV] Lower llvm.trap and llvm.debugtrap

[Sam Elliott via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7214f7a79f4b: [RISCV] Lower llvm.trap and llvm.debugtrap (authored by lenary).
Herald added a subscriber: sameer.abuasal.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69390/new/

https://reviews.llvm.org/D69390

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/intrinsics/trap.ll


Index: llvm/test/CodeGen/RISCV/intrinsics/trap.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/intrinsics/trap.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+; Verify that we lower @llvm.trap() and @llvm.debugtrap() correctly.
+
+declare void @llvm.trap()
+declare void @llvm.debugtrap()
+
+define void @test_trap() nounwind {
+; RV32I-LABEL: test_trap:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    unimp
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test_trap:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    unimp
+; RV64I-NEXT:    ret
+  tail call void @llvm.trap()
+  ret void
+}
+
+define void @test_debugtrap() nounwind {
+; RV32I-LABEL: test_debugtrap:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ebreak
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test_debugtrap:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    ebreak
+; RV64I-NEXT:    ret
+  tail call void @llvm.debugtrap()
+  ret void
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1097,6 +1097,16 @@
 mayLoad = 0, mayStore = 0, hasNoSchedulingInfo = 1 in
 def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [], "", "">;
 
+/// traps
+
+// We lower `trap` to `unimp`, as this causes a hard exception on nearly all
+// systems.
+def : Pat<(trap), (UNIMP)>;
+
+// We lower `debugtrap` to `ebreak`, as this will get the attention of the
+// debugger if possible.
+def : Pat<(debugtrap), (EBREAK)>;
+
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -193,6 +193,9 @@
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
                      Subtarget.is64Bit() ? Legal : Custom);
 
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
+  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
+
   if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
     setMinCmpXchgSizeInBits(32);


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