[llvm] b8042db - [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 28 05:16:10 PDT 2019
Author: Dmitry Preobrazhensky
Date: 2019-10-28T15:03:43+03:00
New Revision: b8042dbe2bbf129cb524fca7a48737e99d1e46bc
URL: https://github.com/llvm/llvm-project/commit/b8042dbe2bbf129cb524fca7a48737e99d1e46bc
DIFF: https://github.com/llvm/llvm-project/commit/b8042dbe2bbf129cb524fca7a48737e99d1e46bc.diff
LOG: [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64
See https://bugs.llvm.org/show_bug.cgi?id=43747
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D69348
Added:
Modified:
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/test/MC/AMDGPU/gfx10_asm_all.s
llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 605425972b1c..db8b8be843b3 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -497,11 +497,11 @@ def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32
} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
-let SubtargetPredicate = isGFX8GFX9 in {
+let SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC] in {
def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
-} // End SubtargetPredicate = isGFX8GFX9
+} // End SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC]
let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in {
@@ -770,6 +770,10 @@ defm V_SUB_NC_I32 :
defm V_ADD_NC_I32 :
VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32_gfx9", "v_add_nc_i32">;
+defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>;
+defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>;
+defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>;
+
defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>;
defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>;
defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>;
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_all.s b/llvm/test/MC/AMDGPU/gfx10_asm_all.s
index c358482eaa38..6ee18e8f34dc 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_all.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_all.s
@@ -131119,3 +131119,135 @@ v_cmp_tru_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
v_cmp_tru_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x26]
// W64-ERR: error: {{instruction not supported on this GPU|invalid operand for instruction}}
+
+v_interp_p1_f32_e64 v5, v2, attr0.x
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v255, v2, attr0.x
+// GFX10: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr1.x
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x00,0xd6,0x01,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr31.x
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x00,0xd6,0x1f,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr32.x
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x00,0xd6,0x20,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v255, attr0.x
+// GFX10: v_interp_p1_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0xfe,0x03,0x00]
+
+v_interp_p1_f32_e64 v5, -v2, attr0.x
+// GFX10: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x40]
+
+v_interp_p1_f32_e64 v5, |v2|, attr0.x
+// GFX10: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x00,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.y
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x00,0xd6,0x40,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.z
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x00,0xd6,0x80,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.w
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x00,0xd6,0xc0,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x clamp
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x00,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x08]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:4
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x10]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x div:2
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x18]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v255, v2, attr0.x
+// GFX10: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr1.x
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x01,0xd6,0x01,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr31.x
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x01,0xd6,0x1f,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr32.x
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x01,0xd6,0x20,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v255, attr0.x
+// GFX10: v_interp_p2_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0xfe,0x03,0x00]
+
+v_interp_p2_f32_e64 v5, -v2, attr0.x
+// GFX10: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x40]
+
+v_interp_p2_f32_e64 v5, |v2|, attr0.x
+// GFX10: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x01,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.y
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x01,0xd6,0x40,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.z
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x01,0xd6,0x80,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.w
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x01,0xd6,0xc0,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x clamp
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x01,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x mul:2
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x08]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x mul:4
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x10]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x div:2
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x18]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v255, p10, attr0.x
+// GFX10: v_interp_mov_f32_e64 v255, p10, attr0.x ; encoding: [0xff,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr1.x
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr1.x ; encoding: [0x05,0x00,0x02,0xd6,0x01,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr31.x
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr31.x ; encoding: [0x05,0x00,0x02,0xd6,0x1f,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr32.x
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x02,0xd6,0x20,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p20, attr0.x
+// GFX10: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x02,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p0, attr0.x
+// GFX10: v_interp_mov_f32_e64 v5, p0, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x04,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.y
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.y ; encoding: [0x05,0x00,0x02,0xd6,0x40,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.z
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.z ; encoding: [0x05,0x00,0x02,0xd6,0x80,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.w
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x02,0xd6,0xc0,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x clamp
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x02,0xd6,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x08]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x10]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x div:2
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x18]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
index 2efdedfd37c2..cc342f9809fd 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -98852,3 +98852,135 @@
# GFX10: v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06]
0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
+0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
+0xff 0x00 0x00 0xd6 0x00 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x00,0xd6,0x01,0x04,0x02,0x00]
+0x05 0x00 0x00 0xd6 0x01 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x00,0xd6,0x1f,0x04,0x02,0x00]
+0x05 0x00 0x00 0xd6 0x1f 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x00,0xd6,0x20,0x04,0x02,0x00]
+0x05 0x00 0x00 0xd6 0x20 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0xfe,0x03,0x00]
+0x05 0x00 0x00 0xd6 0x00 0xfe 0x03 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x40]
+0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x40
+
+# GFX10: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x00,0xd6,0x00,0x04,0x02,0x00]
+0x05 0x02 0x00 0xd6 0x00 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x00,0xd6,0x40,0x04,0x02,0x00]
+0x05 0x00 0x00 0xd6 0x40 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x00,0xd6,0x80,0x04,0x02,0x00]
+0x05 0x00 0x00 0xd6 0x80 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x00,0xd6,0xc0,0x04,0x02,0x00]
+0x05 0x00 0x00 0xd6 0xc0 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x00,0xd6,0x00,0x04,0x02,0x00]
+0x05 0x80 0x00 0xd6 0x00 0x04 0x02 0x00
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x08]
+0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x08
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x10]
+0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x10
+
+# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x18]
+0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x18
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
+0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
+0xff 0x00 0x01 0xd6 0x00 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x01,0xd6,0x01,0x04,0x02,0x00]
+0x05 0x00 0x01 0xd6 0x01 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x01,0xd6,0x1f,0x04,0x02,0x00]
+0x05 0x00 0x01 0xd6 0x1f 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x01,0xd6,0x20,0x04,0x02,0x00]
+0x05 0x00 0x01 0xd6 0x20 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0xfe,0x03,0x00]
+0x05 0x00 0x01 0xd6 0x00 0xfe 0x03 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x40]
+0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x40
+
+# GFX10: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x01,0xd6,0x00,0x04,0x02,0x00]
+0x05 0x02 0x01 0xd6 0x00 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x01,0xd6,0x40,0x04,0x02,0x00]
+0x05 0x00 0x01 0xd6 0x40 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x01,0xd6,0x80,0x04,0x02,0x00]
+0x05 0x00 0x01 0xd6 0x80 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x01,0xd6,0xc0,0x04,0x02,0x00]
+0x05 0x00 0x01 0xd6 0xc0 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x01,0xd6,0x00,0x04,0x02,0x00]
+0x05 0x80 0x01 0xd6 0x00 0x04 0x02 0x00
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x08]
+0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x08
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x10]
+0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x10
+
+# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x18]
+0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x18
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
+0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v255, p10, attr0.x ; encoding: [0xff,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
+0xff 0x00 0x02 0xd6 0x00 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr1.x ; encoding: [0x05,0x00,0x02,0xd6,0x01,0x00,0x00,0x00]
+0x05 0x00 0x02 0xd6 0x01 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr31.x ; encoding: [0x05,0x00,0x02,0xd6,0x1f,0x00,0x00,0x00]
+0x05 0x00 0x02 0xd6 0x1f 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x02,0xd6,0x20,0x00,0x00,0x00]
+0x05 0x00 0x02 0xd6 0x20 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x02,0x00,0x00]
+0x05 0x00 0x02 0xd6 0x00 0x02 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p0, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x04,0x00,0x00]
+0x05 0x00 0x02 0xd6 0x00 0x04 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.y ; encoding: [0x05,0x00,0x02,0xd6,0x40,0x00,0x00,0x00]
+0x05 0x00 0x02 0xd6 0x40 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.z ; encoding: [0x05,0x00,0x02,0xd6,0x80,0x00,0x00,0x00]
+0x05 0x00 0x02 0xd6 0x80 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x02,0xd6,0xc0,0x00,0x00,0x00]
+0x05 0x00 0x02 0xd6 0xc0 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x02,0xd6,0x00,0x00,0x00,0x00]
+0x05 0x80 0x02 0xd6 0x00 0x00 0x00 0x00
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x08]
+0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x08
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x10]
+0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x10
+
+# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x18]
+0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x18
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