[PATCH] D69392: [ARM] MVE interleaving load and stores.
Sam Parker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 28 04:26:35 PDT 2019
samparker added inline comments.
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:16718
// the vector types are divisible by 128.
- if (!Subtarget->hasNEON() || !isLegalInterleavedAccessType(VecTy, DL))
+ if (!isLegalInterleavedAccessType(Factor, VecTy, DL))
return false;
----------------
What is Factor here? Is it not the number of elements..?
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:16774
+ Ops.push_back(Builder.CreateBitCast(BaseAddr, VecEltTy));
+ dbgs() << *BaseAddr << "\n";
+ return Builder.CreateCall(VldnFunc, Ops, "vldN");
----------------
debug
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:16943
+ Ops.push_back(S);
+ Ops.push_back(Builder.getInt32(0));
+ Builder.CreateCall(VstNFunc, Ops);
----------------
How about performing this with a loop?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D69392/new/
https://reviews.llvm.org/D69392
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