[PATCH] D64630: [DebugInfo] Address performance regression with r364515

[Adrian Prantl via Phabricator via llvm-commits]

aprantl added inline comments.


================
Comment at: lib/CodeGen/RegisterCoalescer.cpp:1978
+// See comment for CheckDbgValuesInBlock; this is a specialised copy for
+// when one coalesced register is a physical register.
+static void CheckDbgValuesInBlockForPhysReg(const SlotIndexes &Slots,
----------------
///


================
Comment at: lib/CodeGen/RegisterCoalescer.cpp:2003
+    // Is this a DBG_VALUE for Reg, where Reg is dead?
+    if (MI.isDebugValue() && !RegIsLive &&
+        MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == Reg) {
----------------
if (MI.isDebugValue()) {
  if (!RegIsLive &&MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == Reg) {
  }
  return;
}
// If not, update current liveness record.
SlotIndex Slot = Slots.getInstructionIndex(MI);


================
Comment at: lib/CodeGen/RegisterCoalescer.cpp:2015
+
+  return;
+}
----------------
return is redundant


================
Comment at: lib/CodeGen/RegisterCoalescer.cpp:3362
+// at a particular location. This is to work around the fact that slot-index
+// queries for DBG_VALUEs is slow.
+static void CheckDbgValuesInBlock(const SlotIndexes &Slots,
----------------
///


================
Comment at: lib/CodeGen/RegisterCoalescer.cpp:3391
+  bool RegIsLive = RegLiveness.liveAt(BlockStart);
+  bool OtherIsLive = OtherLiveness.liveAt(BlockStart);
+
----------------
This has so much identical boilerplate with CheckDbgValuesInBlockForPhysReg that I wonder if it should be a generalized version that takes a std::function for code that is different? 


Repository:
  rL LLVM

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  https://reviews.llvm.org/D64630/new/

https://reviews.llvm.org/D64630