[PATCH] D57504: RFC: Prototype & Roadmap for vector predication in LLVM

Shawn Landden via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 24 18:43:27 PDT 2019


shawnl added a comment.

Are predicated vector instructions not just a special case of DemandedBits? Why can't we leave out the .vp. intrinsics, and just generate the predicate with DemandedBits? That way you do a predicated vector operation like so (in zig): As the example makes clear, this optimization would have to be guaranteed in order for the generated code to be correct (as the predicate avoids a divide-by-zero error).

var notzero = v != 0;
if (std.vector.any(notzero)) {

  v = std.vector.select(5 / v, v, notzero);

}


Repository:
  rL LLVM

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https://reviews.llvm.org/D57504





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