[PATCH] D66871: [SVE] MVT scalable size queries

[Graham Hunter via Phabricator via llvm-commits]

huntergr updated this revision to Diff 226410.
huntergr added a comment.
Herald added subscribers: jsji, atanasyan, jrtc27, kbarton, nemanjai, sdardis, jholewinski.

- Refactored to match the same approach used in D53137 <https://reviews.llvm.org/D53137> -- TypeSize returned for all size queries instead of introducing separate interfaces and relying on implicit conversion to be (mostly) compatible with existing code.
- Added 'isByteSized()' interface to TypeSize.
- Minor bugfix to DAGCombiner::ForwardStoreValueToDirectLoad, where implicit conversions allowed an unsigned number to wrap and then be converted to a larger signed integer; with TypeSize using uint64_t instead, this showed up during a `make check-all` run with ubsan active. Can't write a test for that one since the transform bailed out when Offset was non-zero.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66871/new/

https://reviews.llvm.org/D66871

Files:
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/include/llvm/CodeGen/ValueTypes.h
  llvm/include/llvm/Support/MachineValueType.h
  llvm/include/llvm/Support/TypeSize.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/ValueTypes.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64StackOffset.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
  llvm/utils/TableGen/CodeGenDAGPatterns.cpp

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