[PATCH] D69247: [AArch64][Builtins] Avoid unnecssary cache cleaning

[Peter Smith via Phabricator via llvm-commits]

peter.smith added a comment.

I'm on vacation at the moment, will take a look next week as this will need some checking of the architecture manual. This LKML message https://lkml.org/lkml/2018/10/9/698 implies that in some cases it is insufficient to just read CTR_EL0.{IDC,DIC}, as a 0 also requires a check with CTR_EL1 which can't be done in userspace. Would you be able to take a look at that thread? For compiler-rt we need something that works on all CPUs at EL0.


Repository:
  rCRT Compiler Runtime

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  https://reviews.llvm.org/D69247/new/

https://reviews.llvm.org/D69247