[PATCH] D69246: [RISCV] Add support for half-precision floats

[Luís Marques via Phabricator via llvm-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary.
Herald added subscribers: llvm-commits, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

Most fp16 operations are automatically supported by promoting the half-precision values to single-precision ones. This patch completes fp16 support by ensuring that load extension / truncate store operations are properly expanded.

The tests included in the patch check the load ext / trunc store behavior, and add a few sanity checks for promoted fp16 operations. Testing with riscv32 using the ilp32d ABI is enough to check the 4 ext/trunc cases, and the riscv64 output doesn't differ in any important way, so the tests target only riscv32.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69246

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/fp16-promote.ll

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