[PATCH] D69333: [MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, urem

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: atanasyan, petarj.
Herald added subscribers: llvm-commits, jrtc27, hiraditya, arichardson, rovka, sdardis.
Herald added a project: LLVM.

Select vector G_SDIV G_SREM G_UDIV G_UREM for MIPS32 with MSA. We have
to set bank for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_div_s_<format>, __builtin_msa_mod_s_<format>,
__builtin_msa_div_u_<format> and __builtin_msa_mod_u_<format> will be 
transformed into G_SDIV G_SREM G_UDIV G_UREM in legalizeIntrinsic 
respectively and selected in the same way.


Repository:
  rL LLVM

https://reviews.llvm.org/D69333

Files:
  llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div_vec.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div_vec_builtin.ll
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D69333.226117.patch
Type: text/x-patch
Size: 99837 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191023/c26e8c9a/attachment.bin>