[llvm] d1815da - [MIPS GlobalISel] Select MSA vector generic and builtin mul
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 23 02:25:05 PDT 2019
Author: Petar Avramovic
Date: 2019-10-23T11:22:07+02:00
New Revision: d1815dacb00d2f5845449a20f6e749119962aa87
URL: https://github.com/llvm/llvm-project/commit/d1815dacb00d2f5845449a20f6e749119962aa87
DIFF: https://github.com/llvm/llvm-project/commit/d1815dacb00d2f5845449a20f6e749119962aa87.diff
LOG: [MIPS GlobalISel] Select MSA vector generic and builtin mul
Select vector G_MUL for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
Manual selection of G_MUL is now done for gprb only.
__builtin_msa_mulv_<format> will be transformed into G_MUL
in legalizeIntrinsic and selected in the same way.
Differential Revision: https://reviews.llvm.org/D69310
Added:
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
Modified:
llvm/lib/Target/Mips/MipsInstructionSelector.cpp
llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index f8fc7cb0898b..9952b5c45882 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -239,7 +239,9 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
return true;
}
- if (I.getOpcode() == Mips::G_MUL) {
+ if (I.getOpcode() == Mips::G_MUL &&
+ (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() ==
+ Mips::GPRBRegBankID)) {
MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
.add(I.getOperand(0))
.add(I.getOperand(1))
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index ce203b39929c..3c931d77e941 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -61,11 +61,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
const LLT v2s64 = LLT::vector(2, 64);
const LLT p0 = LLT::pointer(0, 32);
- getActionDefinitionsBuilder(G_MUL)
- .legalFor({s32})
- .clampScalar(0, s32, s32);
-
- getActionDefinitionsBuilder({G_ADD, G_SUB})
+ getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
.legalIf([=, &ST](const LegalityQuery &Query) {
if (CheckTyN(0, Query, {s32}))
return true;
@@ -377,6 +373,11 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
case Intrinsic::mips_subvi_d:
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
+ case Intrinsic::mips_mulv_b:
+ case Intrinsic::mips_mulv_h:
+ case Intrinsic::mips_mulv_w:
+ case Intrinsic::mips_mulv_d:
+ return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
default:
break;
}
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index 51a1cf3fa48f..f8531f888568 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -437,7 +437,6 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
switch (Opc) {
case G_TRUNC:
- case G_MUL:
case G_UMULH:
case G_ZEXTLOAD:
case G_SEXTLOAD:
@@ -460,6 +459,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
case G_ADD:
case G_SUB:
+ case G_MUL:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
if (Op0Size == 128)
OperandsMapping = getMSAMapping(MF);
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
new file mode 100644
index 000000000000..b69f8c3abe6d
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
@@ -0,0 +1,130 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+ define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
+ define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
+ define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
+ define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
+
+...
+---
+name: mul_v16i8
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v16i8
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
+ ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
+ ; P5600: [[MULV_B:%[0-9]+]]:msa128b = MULV_B [[LD_B1]], [[LD_B]]
+ ; P5600: ST_B [[MULV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(p0) = COPY $a2
+ %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:fprb(<16 x s8>) = G_MUL %4, %3
+ G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v8i16
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v8i16
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a)
+ ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)
+ ; P5600: [[MULV_H:%[0-9]+]]:msa128h = MULV_H [[LD_H1]], [[LD_H]]
+ ; P5600: ST_H [[MULV_H]], [[COPY2]], 0 :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(p0) = COPY $a2
+ %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:fprb(<8 x s16>) = G_MUL %4, %3
+ G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v4i32
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v4i32
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
+ ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
+ ; P5600: [[MULV_W:%[0-9]+]]:msa128w = MULV_W [[LD_W1]], [[LD_W]]
+ ; P5600: ST_W [[MULV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(p0) = COPY $a2
+ %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:fprb(<4 x s32>) = G_MUL %4, %3
+ G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v2i64
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v2i64
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a)
+ ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
+ ; P5600: [[MULV_D:%[0-9]+]]:msa128d = MULV_D [[LD_D1]], [[LD_D]]
+ ; P5600: ST_D [[MULV_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(p0) = COPY $a2
+ %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:fprb(<2 x s64>) = G_MUL %4, %3
+ G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
new file mode 100644
index 000000000000..9e9149363cfd
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
@@ -0,0 +1,122 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+ define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
+ define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
+ define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
+ define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
+
+...
+---
+name: mul_v16i8
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v16i8
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<16 x s8>) = G_MUL %4, %3
+ G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v8i16
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v8i16
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<8 x s16>) = G_MUL %4, %3
+ G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v4i32
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v4i32
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<4 x s32>) = G_MUL %4, %3
+ G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v2i64
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v2i64
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<2 x s64>) = G_MUL %4, %3
+ G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
new file mode 100644
index 000000000000..6019a62d0744
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
@@ -0,0 +1,129 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+ declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>)
+ define void @mul_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
+
+ declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>)
+ define void @mul_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
+
+ declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>)
+ define void @mul_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
+
+ declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>)
+ define void @mul_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
+
+...
+---
+name: mul_v16i8_builtin
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v16i8_builtin
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[LOAD]], [[LOAD1]]
+ ; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.b), %3(<16 x s8>), %4(<16 x s8>)
+ G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v8i16_builtin
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v8i16_builtin
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[LOAD]], [[LOAD1]]
+ ; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.h), %3(<8 x s16>), %4(<8 x s16>)
+ G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v4i32_builtin
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v4i32_builtin
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LOAD]], [[LOAD1]]
+ ; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.w), %3(<4 x s32>), %4(<4 x s32>)
+ G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v2i64_builtin
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v2i64_builtin
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[LOAD]], [[LOAD1]]
+ ; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.d), %3(<2 x s64>), %4(<2 x s64>)
+ G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
new file mode 100644
index 000000000000..d3f085c239fd
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
+
+define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
+; P5600-LABEL: mul_v16i8:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.b $w0, 0($4)
+; P5600-NEXT: ld.b $w1, 0($5)
+; P5600-NEXT: mulv.b $w0, $w1, $w0
+; P5600-NEXT: st.b $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %a, align 16
+ %1 = load <16 x i8>, <16 x i8>* %b, align 16
+ %mul = mul <16 x i8> %1, %0
+ store <16 x i8> %mul, <16 x i8>* %c, align 16
+ ret void
+}
+
+define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
+; P5600-LABEL: mul_v8i16:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.h $w0, 0($4)
+; P5600-NEXT: ld.h $w1, 0($5)
+; P5600-NEXT: mulv.h $w0, $w1, $w0
+; P5600-NEXT: st.h $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <8 x i16>, <8 x i16>* %a, align 16
+ %1 = load <8 x i16>, <8 x i16>* %b, align 16
+ %mul = mul <8 x i16> %1, %0
+ store <8 x i16> %mul, <8 x i16>* %c, align 16
+ ret void
+}
+
+define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
+; P5600-LABEL: mul_v4i32:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.w $w0, 0($4)
+; P5600-NEXT: ld.w $w1, 0($5)
+; P5600-NEXT: mulv.w $w0, $w1, $w0
+; P5600-NEXT: st.w $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <4 x i32>, <4 x i32>* %a, align 16
+ %1 = load <4 x i32>, <4 x i32>* %b, align 16
+ %mul = mul <4 x i32> %1, %0
+ store <4 x i32> %mul, <4 x i32>* %c, align 16
+ ret void
+}
+
+define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
+; P5600-LABEL: mul_v2i64:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.d $w0, 0($4)
+; P5600-NEXT: ld.d $w1, 0($5)
+; P5600-NEXT: mulv.d $w0, $w1, $w0
+; P5600-NEXT: st.d $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <2 x i64>, <2 x i64>* %a, align 16
+ %1 = load <2 x i64>, <2 x i64>* %b, align 16
+ %mul = mul <2 x i64> %1, %0
+ store <2 x i64> %mul, <2 x i64>* %c, align 16
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll
new file mode 100644
index 000000000000..0e5be50320c0
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
+
+declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>)
+define void @mul_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
+; P5600-LABEL: mul_v16i8_builtin:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.b $w0, 0($4)
+; P5600-NEXT: ld.b $w1, 0($5)
+; P5600-NEXT: mulv.b $w0, $w0, $w1
+; P5600-NEXT: st.b $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %a, align 16
+ %1 = load <16 x i8>, <16 x i8>* %b, align 16
+ %2 = tail call <16 x i8> @llvm.mips.mulv.b(<16 x i8> %0, <16 x i8> %1)
+ store <16 x i8> %2, <16 x i8>* %c, align 16
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>)
+define void @mul_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
+; P5600-LABEL: mul_v8i16_builtin:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.h $w0, 0($4)
+; P5600-NEXT: ld.h $w1, 0($5)
+; P5600-NEXT: mulv.h $w0, $w0, $w1
+; P5600-NEXT: st.h $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <8 x i16>, <8 x i16>* %a, align 16
+ %1 = load <8 x i16>, <8 x i16>* %b, align 16
+ %2 = tail call <8 x i16> @llvm.mips.mulv.h(<8 x i16> %0, <8 x i16> %1)
+ store <8 x i16> %2, <8 x i16>* %c, align 16
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>)
+define void @mul_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
+; P5600-LABEL: mul_v4i32_builtin:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.w $w0, 0($4)
+; P5600-NEXT: ld.w $w1, 0($5)
+; P5600-NEXT: mulv.w $w0, $w0, $w1
+; P5600-NEXT: st.w $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <4 x i32>, <4 x i32>* %a, align 16
+ %1 = load <4 x i32>, <4 x i32>* %b, align 16
+ %2 = tail call <4 x i32> @llvm.mips.mulv.w(<4 x i32> %0, <4 x i32> %1)
+ store <4 x i32> %2, <4 x i32>* %c, align 16
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>)
+define void @mul_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
+; P5600-LABEL: mul_v2i64_builtin:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.d $w0, 0($4)
+; P5600-NEXT: ld.d $w1, 0($5)
+; P5600-NEXT: mulv.d $w0, $w0, $w1
+; P5600-NEXT: st.d $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <2 x i64>, <2 x i64>* %a, align 16
+ %1 = load <2 x i64>, <2 x i64>* %b, align 16
+ %2 = tail call <2 x i64> @llvm.mips.mulv.d(<2 x i64> %0, <2 x i64> %1)
+ store <2 x i64> %2, <2 x i64>* %c, align 16
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
new file mode 100644
index 000000000000..5daa4a782be9
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
@@ -0,0 +1,126 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+ define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
+ define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
+ define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
+ define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
+
+...
+---
+name: mul_v16i8
+alignment: 4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v16i8
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:fprb(<16 x s8>) = G_MUL [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<16 x s8>) = G_MUL %4, %3
+ G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v8i16
+alignment: 4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v8i16
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:fprb(<8 x s16>) = G_MUL [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<8 x s16>) = G_MUL %4, %3
+ G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v4i32
+alignment: 4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v4i32
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:fprb(<4 x s32>) = G_MUL [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<4 x s32>) = G_MUL %4, %3
+ G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: mul_v2i64
+alignment: 4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: mul_v2i64
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[MUL:%[0-9]+]]:fprb(<2 x s64>) = G_MUL [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<2 x s64>) = G_MUL %4, %3
+ G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
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