[llvm] e4af9de - [MIPS GlobalISel] Select MSA vector generic and builtin add
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 22 06:50:36 PDT 2019
Author: Petar Avramovic
Date: 2019-10-22T13:51:57Z
New Revision: e4af9de36ca60483040af381edd10e716e7b077d
URL: https://github.com/llvm/llvm-project/commit/e4af9de36ca60483040af381edd10e716e7b077d
DIFF: https://github.com/llvm/llvm-project/commit/e4af9de36ca60483040af381edd10e716e7b077d.diff
LOG: [MIPS GlobalISel] Select MSA vector generic and builtin add
Select vector G_ADD for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_addv_<format> will be transformed into G_ADD
in legalizeIntrinsic and selected in the same way.
__builtin_msa_addvi_<format> will be directly selected into
ADDVI_<format> in legalizeIntrinsic. MIR tests for it have
unnecessary additional copies. Capture current state of tests
with run-pass=legalizer with a test in test/CodeGen/MIR/Mips.
Differential Revision: https://reviews.llvm.org/D68984
llvm-svn: 375501
Added:
llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
Modified:
llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index 96706d3b3966..bb4a1d902d75 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -41,6 +41,14 @@ CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
return false;
}
+static bool CheckTyN(unsigned N, const LegalityQuery &Query,
+ std::initializer_list<LLT> SupportedValues) {
+ for (auto &Val : SupportedValues)
+ if (Val == Query.Types[N])
+ return true;
+ return false;
+}
+
MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
using namespace TargetOpcode;
@@ -53,10 +61,20 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
const LLT v2s64 = LLT::vector(2, 64);
const LLT p0 = LLT::pointer(0, 32);
- getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
+ getActionDefinitionsBuilder({G_SUB, G_MUL})
.legalFor({s32})
.clampScalar(0, s32, s32);
+ getActionDefinitionsBuilder(G_ADD)
+ .legalIf([=, &ST](const LegalityQuery &Query) {
+ if (CheckTyN(0, Query, {s32}))
+ return true;
+ if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
+ return true;
+ return false;
+ })
+ .clampScalar(0, s32, s32);
+
getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
.lowerFor({{s32, s1}});
@@ -270,6 +288,33 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
return true;
}
+static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,
+ MachineIRBuilder &MIRBuilder,
+ const MipsSubtarget &ST) {
+ assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
+ if (!MIRBuilder.buildInstr(Opcode)
+ .add(MI.getOperand(0))
+ .add(MI.getOperand(2))
+ .add(MI.getOperand(3))
+ .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(),
+ *ST.getRegBankInfo()))
+ return false;
+ MI.eraseFromParent();
+ return true;
+}
+
+static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
+ MachineIRBuilder &MIRBuilder,
+ const MipsSubtarget &ST) {
+ assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
+ MIRBuilder.buildInstr(Opcode)
+ .add(MI.getOperand(0))
+ .add(MI.getOperand(2))
+ .add(MI.getOperand(3));
+ MI.eraseFromParent();
+ return true;
+}
+
bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const {
@@ -306,6 +351,19 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
MI.eraseFromParent();
return true;
}
+ case Intrinsic::mips_addv_b:
+ case Intrinsic::mips_addv_h:
+ case Intrinsic::mips_addv_w:
+ case Intrinsic::mips_addv_d:
+ return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST);
+ case Intrinsic::mips_addvi_b:
+ return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
+ case Intrinsic::mips_addvi_h:
+ return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
+ case Intrinsic::mips_addvi_w:
+ return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
+ case Intrinsic::mips_addvi_d:
+ return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
default:
break;
}
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index a203ab5081af..d334366e727c 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -437,7 +437,6 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
switch (Opc) {
case G_TRUNC:
- case G_ADD:
case G_SUB:
case G_MUL:
case G_UMULH:
@@ -460,6 +459,11 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_VASTART:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
break;
+ case G_ADD:
+ OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
+ if (Op0Size == 128)
+ OperandsMapping = getMSAMapping(MF);
+ break;
case G_STORE:
case G_LOAD:
if (Op0Size == 128) {
diff --git a/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
new file mode 100644
index 000000000000..71329fd45b5d
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -stop-after=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+
+; Check there are no COPY instructions surrounding ADDVI_W instruction.
+; All virtual registers were created with createGenericVirtualRegister
+; which sets RegClassOrRegBank in VRegInfo.
+; Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
+; gets selected into ADDVI_W works as expected.
+; Check that setRegClassOrRegBank.mir has same output.
+
+declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
+define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
+ ; P5600-LABEL: name: add_v4i32_builtin_imm
+ ; P5600: bb.1.entry:
+ ; P5600: liveins: $a0, $a1
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
+ ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+entry:
+ %0 = load <4 x i32>, <4 x i32>* %a, align 16
+ %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
+ store <4 x i32> %1, <4 x i32>* %c, align 16
+ ret void
+}
diff --git a/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
new file mode 100644
index 000000000000..2645c97095ea
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
@@ -0,0 +1,41 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+
+# Check there are COPY instructions surrounding ADDVI_W instruction.
+# MIParser does not set RegClassOrRegBank for parsed virtual registers.
+# Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
+# gets selected into ADDVI_W creates additional copies.
+# FixMe: Make sure this test has same output as setRegClassOrRegBank.ll.
+
+--- |
+
+ declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
+ define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
+
+...
+---
+name: add_v4i32_builtin_imm
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; P5600-LABEL: name: add_v4i32_builtin_imm
+ ; P5600: liveins: $a0, $a1
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
+ ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
+ ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
+ ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
+ G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
new file mode 100644
index 000000000000..6903f01ae5ad
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
@@ -0,0 +1,130 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+ define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
+ define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
+ define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
+ define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
+
+...
+---
+name: add_v16i8
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v16i8
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
+ ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
+ ; P5600: [[ADDV_B:%[0-9]+]]:msa128b = ADDV_B [[LD_B1]], [[LD_B]]
+ ; P5600: ST_B [[ADDV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(p0) = COPY $a2
+ %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:fprb(<16 x s8>) = G_ADD %4, %3
+ G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v8i16
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v8i16
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a)
+ ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)
+ ; P5600: [[ADDV_H:%[0-9]+]]:msa128h = ADDV_H [[LD_H1]], [[LD_H]]
+ ; P5600: ST_H [[ADDV_H]], [[COPY2]], 0 :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(p0) = COPY $a2
+ %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:fprb(<8 x s16>) = G_ADD %4, %3
+ G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v4i32
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v4i32
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
+ ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
+ ; P5600: [[ADDV_W:%[0-9]+]]:msa128w = ADDV_W [[LD_W1]], [[LD_W]]
+ ; P5600: ST_W [[ADDV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(p0) = COPY $a2
+ %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:fprb(<4 x s32>) = G_ADD %4, %3
+ G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v2i64
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v2i64
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a)
+ ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
+ ; P5600: [[ADDV_D:%[0-9]+]]:msa128d = ADDV_D [[LD_D1]], [[LD_D]]
+ ; P5600: ST_D [[ADDV_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(p0) = COPY $a2
+ %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:fprb(<2 x s64>) = G_ADD %4, %3
+ G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
new file mode 100644
index 000000000000..d0950ea638f8
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
@@ -0,0 +1,122 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+ define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
+ define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
+ define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
+ define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
+
+...
+---
+name: add_v16i8
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v16i8
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<16 x s8>) = G_ADD %4, %3
+ G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v8i16
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v8i16
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<8 x s16>) = G_ADD %4, %3
+ G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v4i32
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v4i32
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<4 x s32>) = G_ADD %4, %3
+ G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v2i64
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v2i64
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<2 x s64>) = G_ADD %4, %3
+ G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
new file mode 100644
index 000000000000..2e71669bc9d0
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
@@ -0,0 +1,245 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+ declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>)
+ define void @add_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
+
+ declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>)
+ define void @add_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
+
+ declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>)
+ define void @add_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
+
+ declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>)
+ define void @add_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
+
+ declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32 immarg)
+ define void @add_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) { entry: ret void }
+
+ declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32 immarg)
+ define void @add_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) { entry: ret void }
+
+ declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
+ define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
+
+ declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32 immarg)
+ define void @add_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) { entry: ret void }
+
+...
+---
+name: add_v16i8_builtin
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v16i8_builtin
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD]], [[LOAD1]]
+ ; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addv.b), %3(<16 x s8>), %4(<16 x s8>)
+ G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v8i16_builtin
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v8i16_builtin
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD]], [[LOAD1]]
+ ; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addv.h), %3(<8 x s16>), %4(<8 x s16>)
+ G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v4i32_builtin
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v4i32_builtin
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD]], [[LOAD1]]
+ ; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addv.w), %3(<4 x s32>), %4(<4 x s32>)
+ G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v2i64_builtin
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v2i64_builtin
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD]], [[LOAD1]]
+ ; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addv.d), %3(<2 x s64>), %4(<2 x s64>)
+ G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v16i8_builtin_imm
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; P5600-LABEL: name: add_v16i8_builtin_imm
+ ; P5600: liveins: $a0, $a1
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[COPY2:%[0-9]+]]:msa128b = COPY [[LOAD]](<16 x s8>)
+ ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b = ADDVI_B [[COPY2]], 3
+ ; P5600: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ADDVI_B]]
+ ; P5600: G_STORE [[COPY3]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %3:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.b), %2(<16 x s8>), 3
+ G_STORE %3(<16 x s8>), %1(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v8i16_builtin_imm
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; P5600-LABEL: name: add_v8i16_builtin_imm
+ ; P5600: liveins: $a0, $a1
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[COPY2:%[0-9]+]]:msa128h = COPY [[LOAD]](<8 x s16>)
+ ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h = ADDVI_H [[COPY2]], 18
+ ; P5600: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ADDVI_H]]
+ ; P5600: G_STORE [[COPY3]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %3:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.h), %2(<8 x s16>), 18
+ G_STORE %3(<8 x s16>), %1(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v4i32_builtin_imm
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; P5600-LABEL: name: add_v4i32_builtin_imm
+ ; P5600: liveins: $a0, $a1
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
+ ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
+ ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
+ ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
+ G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v2i64_builtin_imm
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; P5600-LABEL: name: add_v2i64_builtin_imm
+ ; P5600: liveins: $a0, $a1
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[COPY2:%[0-9]+]]:msa128d = COPY [[LOAD]](<2 x s64>)
+ ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d = ADDVI_D [[COPY2]], 31
+ ; P5600: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ADDVI_D]]
+ ; P5600: G_STORE [[COPY3]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.d), %2(<2 x s64>), 31
+ G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
new file mode 100644
index 000000000000..5d8585173b99
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
+
+define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
+; P5600-LABEL: add_v16i8:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.b $w0, 0($4)
+; P5600-NEXT: ld.b $w1, 0($5)
+; P5600-NEXT: addv.b $w0, $w1, $w0
+; P5600-NEXT: st.b $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %a, align 16
+ %1 = load <16 x i8>, <16 x i8>* %b, align 16
+ %add = add <16 x i8> %1, %0
+ store <16 x i8> %add, <16 x i8>* %c, align 16
+ ret void
+}
+
+define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
+; P5600-LABEL: add_v8i16:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.h $w0, 0($4)
+; P5600-NEXT: ld.h $w1, 0($5)
+; P5600-NEXT: addv.h $w0, $w1, $w0
+; P5600-NEXT: st.h $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <8 x i16>, <8 x i16>* %a, align 16
+ %1 = load <8 x i16>, <8 x i16>* %b, align 16
+ %add = add <8 x i16> %1, %0
+ store <8 x i16> %add, <8 x i16>* %c, align 16
+ ret void
+}
+
+define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
+; P5600-LABEL: add_v4i32:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.w $w0, 0($4)
+; P5600-NEXT: ld.w $w1, 0($5)
+; P5600-NEXT: addv.w $w0, $w1, $w0
+; P5600-NEXT: st.w $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <4 x i32>, <4 x i32>* %a, align 16
+ %1 = load <4 x i32>, <4 x i32>* %b, align 16
+ %add = add <4 x i32> %1, %0
+ store <4 x i32> %add, <4 x i32>* %c, align 16
+ ret void
+}
+
+define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
+; P5600-LABEL: add_v2i64:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.d $w0, 0($4)
+; P5600-NEXT: ld.d $w1, 0($5)
+; P5600-NEXT: addv.d $w0, $w1, $w0
+; P5600-NEXT: st.d $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <2 x i64>, <2 x i64>* %a, align 16
+ %1 = load <2 x i64>, <2 x i64>* %b, align 16
+ %add = add <2 x i64> %1, %0
+ store <2 x i64> %add, <2 x i64>* %c, align 16
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll
new file mode 100644
index 000000000000..ea05479ce2e8
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll
@@ -0,0 +1,138 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
+
+declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>)
+define void @add_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
+; P5600-LABEL: add_v16i8_builtin:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.b $w0, 0($4)
+; P5600-NEXT: ld.b $w1, 0($5)
+; P5600-NEXT: addv.b $w0, $w0, $w1
+; P5600-NEXT: st.b $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %a, align 16
+ %1 = load <16 x i8>, <16 x i8>* %b, align 16
+ %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
+ store <16 x i8> %2, <16 x i8>* %c, align 16
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>)
+define void @add_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
+; P5600-LABEL: add_v8i16_builtin:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.h $w0, 0($4)
+; P5600-NEXT: ld.h $w1, 0($5)
+; P5600-NEXT: addv.h $w0, $w0, $w1
+; P5600-NEXT: st.h $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <8 x i16>, <8 x i16>* %a, align 16
+ %1 = load <8 x i16>, <8 x i16>* %b, align 16
+ %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
+ store <8 x i16> %2, <8 x i16>* %c, align 16
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>)
+define void @add_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
+; P5600-LABEL: add_v4i32_builtin:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.w $w0, 0($4)
+; P5600-NEXT: ld.w $w1, 0($5)
+; P5600-NEXT: addv.w $w0, $w0, $w1
+; P5600-NEXT: st.w $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <4 x i32>, <4 x i32>* %a, align 16
+ %1 = load <4 x i32>, <4 x i32>* %b, align 16
+ %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
+ store <4 x i32> %2, <4 x i32>* %c, align 16
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>)
+define void @add_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
+; P5600-LABEL: add_v2i64_builtin:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.d $w0, 0($4)
+; P5600-NEXT: ld.d $w1, 0($5)
+; P5600-NEXT: addv.d $w0, $w0, $w1
+; P5600-NEXT: st.d $w0, 0($6)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <2 x i64>, <2 x i64>* %a, align 16
+ %1 = load <2 x i64>, <2 x i64>* %b, align 16
+ %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
+ store <2 x i64> %2, <2 x i64>* %c, align 16
+ ret void
+}
+
+declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32 immarg)
+define void @add_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) {
+; P5600-LABEL: add_v16i8_builtin_imm:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.b $w0, 0($4)
+; P5600-NEXT: addvi.b $w0, $w0, 3
+; P5600-NEXT: st.b $w0, 0($5)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %a, align 16
+ %1 = tail call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %0, i32 3)
+ store <16 x i8> %1, <16 x i8>* %c, align 16
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32 immarg)
+define void @add_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) {
+; P5600-LABEL: add_v8i16_builtin_imm:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.h $w0, 0($4)
+; P5600-NEXT: addvi.h $w0, $w0, 18
+; P5600-NEXT: st.h $w0, 0($5)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <8 x i16>, <8 x i16>* %a, align 16
+ %1 = tail call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %0, i32 18)
+ store <8 x i16> %1, <8 x i16>* %c, align 16
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
+define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
+; P5600-LABEL: add_v4i32_builtin_imm:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.w $w0, 0($4)
+; P5600-NEXT: addvi.w $w0, $w0, 25
+; P5600-NEXT: st.w $w0, 0($5)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <4 x i32>, <4 x i32>* %a, align 16
+ %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
+ store <4 x i32> %1, <4 x i32>* %c, align 16
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32 immarg)
+define void @add_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) {
+; P5600-LABEL: add_v2i64_builtin_imm:
+; P5600: # %bb.0: # %entry
+; P5600-NEXT: ld.d $w0, 0($4)
+; P5600-NEXT: addvi.d $w0, $w0, 31
+; P5600-NEXT: st.d $w0, 0($5)
+; P5600-NEXT: jr $ra
+; P5600-NEXT: nop
+entry:
+ %0 = load <2 x i64>, <2 x i64>* %a, align 16
+ %1 = tail call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %0, i32 31)
+ store <2 x i64> %1, <2 x i64>* %c, align 16
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
new file mode 100644
index 000000000000..59fa2a89bf3d
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
@@ -0,0 +1,126 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+ define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
+ define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
+ define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
+ define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
+
+...
+---
+name: add_v16i8
+alignment: 4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v16i8
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:fprb(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<16 x s8>) = G_ADD %4, %3
+ G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v8i16
+alignment: 4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v8i16
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:fprb(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<8 x s16>) = G_ADD %4, %3
+ G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v4i32
+alignment: 4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v4i32
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:fprb(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<4 x s32>) = G_ADD %4, %3
+ G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
+---
+name: add_v2i64
+alignment: 4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1, $a2
+
+ ; P5600-LABEL: name: add_v2i64
+ ; P5600: liveins: $a0, $a1, $a2
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
+ ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
+ ; P5600: [[ADD:%[0-9]+]]:fprb(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
+ ; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
+ ; P5600: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(p0) = COPY $a2
+ %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
+ %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
+ %5:_(<2 x s64>) = G_ADD %4, %3
+ G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
+ RetRA
+
+...
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