[PATCH] D68443: [PowerPC] Spill CR LT bits on P9 using setb

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM aside from a couple of minor nits that can be addressed on the commit.



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Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:781
   default:
+    // On POWER9, spilling LT bits with the setb instruction is more efficient.
+    if (Subtarget.isISA3_0()) {
----------------
I think this would benefit from a slightly more elaborate explanation. Perhaps:
```
// On Power9, we can use SETB to extract the LT bit. This only works for
// the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
// of the bit we care about (32-bit sign bit) will be set to the value of
// the LT bit (regardless of the other bits in the CR field).
```


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Comment at: llvm/test/CodeGen/PowerPC/spill_p9_setb.ll:12
+; CHECK-DAG:    crnor 4*cr[[CREG:.*]]+lt, eq, eq
+; CHECK-NOT:    mfocrf [[REG2:.*]], [[CREG]]
+; CHECK-NOT:    rlwinm [[REG2]], [[REG2]]
----------------
Rather than explicitly checking for the new sequence and not the old sequence, please just add a `RUN` line to this test case that will use `-mcpu=pwr8` and produce the checks with the script.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D68443/new/

https://reviews.llvm.org/D68443