[llvm] r375445 - [X86] Rename matchBitOpReduction to matchScalarReduction. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 21 12:19:51 PDT 2019
Author: rksimon
Date: Mon Oct 21 12:19:50 2019
New Revision: 375445
URL: http://llvm.org/viewvc/llvm-project?rev=375445&view=rev
Log:
[X86] Rename matchBitOpReduction to matchScalarReduction. NFCI.
This doesn't need to be just for bitops, but the ops do need to be fully associative.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=375445&r1=375444&r2=375445&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Oct 21 12:19:50 2019
@@ -19891,8 +19891,8 @@ static SDValue getSETCC(X86::CondCode Co
/// Helper for matching OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1),...))
/// style scalarized (associative) reduction patterns.
-static bool matchBitOpReduction(SDValue Op, ISD::NodeType BinOp,
- SmallVectorImpl<SDValue> &SrcOps) {
+static bool matchScalarReduction(SDValue Op, ISD::NodeType BinOp,
+ SmallVectorImpl<SDValue> &SrcOps) {
SmallVector<SDValue, 8> Opnds;
DenseMap<SDValue, APInt> SrcOpMap;
EVT VT = MVT::Other;
@@ -19965,7 +19965,7 @@ static SDValue LowerVectorAllZeroTest(SD
return SDValue();
SmallVector<SDValue, 8> VecIns;
- if (!matchBitOpReduction(Op, ISD::OR, VecIns))
+ if (!matchScalarReduction(Op, ISD::OR, VecIns))
return SDValue();
// Quit if not 128/256-bit vector.
@@ -39129,7 +39129,7 @@ static SDValue combineAnd(SDNode *N, Sel
// TODO: Support multiple SrcOps.
if (VT == MVT::i1) {
SmallVector<SDValue, 2> SrcOps;
- if (matchBitOpReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
+ if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
SrcOps.size() == 1) {
SDLoc dl(N);
unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();
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