[llvm] r375420 - [NFC] Cleanup with variable name IsPPC64 & IsDarwin
Xiangling Liao via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 21 08:36:13 PDT 2019
Author: xiangling_liao
Date: Mon Oct 21 08:36:13 2019
New Revision: 375420
URL: http://llvm.org/viewvc/llvm-project?rev=375420&view=rev
Log:
[NFC] Cleanup with variable name IsPPC64 & IsDarwin
Clean up PPCAsmPrinter with IsPPC64 and IsDarwin.
Differential Revision: https://reviews.llvm.org/D69259
Modified:
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=375420&r1=375419&r2=375420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon Oct 21 08:36:13 2019
@@ -536,6 +536,7 @@ static MCSymbol *getMCSymbolForTOCPseudo
void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst TmpInst;
const bool IsDarwin = TM.getTargetTriple().isOSDarwin();
+ const bool IsPPC64 = Subtarget->isPPC64();
const bool IsAIX = Subtarget->isAIXABI();
const Module *M = MF->getFunction().getParent();
PICLevel::Level PL = M->getPICLevel();
@@ -759,8 +760,7 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDIStocHA: {
- assert((IsAIX && !Subtarget->isPPC64() &&
- TM.getCodeModel() == CodeModel::Large) &&
+ assert((IsAIX && !IsPPC64 && TM.getCodeModel() == CodeModel::Large) &&
"This pseudo should only be selected for 32-bit large code model on"
" AIX.");
@@ -790,8 +790,7 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::LWZtocL: {
- assert(IsAIX && !Subtarget->isPPC64() &&
- TM.getCodeModel() == CodeModel::Large &&
+ assert(IsAIX && !IsPPC64 && TM.getCodeModel() == CodeModel::Large &&
"This pseudo should only be selected for 32-bit large code model on"
" AIX.");
@@ -921,7 +920,7 @@ void PPCAsmPrinter::EmitInstruction(cons
case PPC::ADDISgotTprelHA: {
// Transform: %xd = ADDISgotTprelHA %x2, @sym
// Into: %xd = ADDIS8 %x2, sym at got@tlsgd at ha
- assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
+ assert(IsPPC64 && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -940,14 +939,13 @@ void PPCAsmPrinter::EmitInstruction(cons
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin);
// Change the opcode to LD.
- TmpInst.setOpcode(Subtarget->isPPC64() ? PPC::LD : PPC::LWZ);
+ TmpInst.setOpcode(IsPPC64 ? PPC::LD : PPC::LWZ);
const MachineOperand &MO = MI->getOperand(1);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *Exp = MCSymbolRefExpr::create(
- MOSymbol,
- Subtarget->isPPC64() ? MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO
- : MCSymbolRefExpr::VK_PPC_GOT_TPREL,
+ MOSymbol, IsPPC64 ? MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO
+ : MCSymbolRefExpr::VK_PPC_GOT_TPREL,
OutContext);
TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
EmitToStreamer(*OutStreamer, TmpInst);
@@ -1001,7 +999,7 @@ void PPCAsmPrinter::EmitInstruction(cons
case PPC::ADDIStlsgdHA: {
// Transform: %xd = ADDIStlsgdHA %x2, @sym
// Into: %xd = ADDIS8 %x2, sym at got@tlsgd at ha
- assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
+ assert(IsPPC64 && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -1024,11 +1022,11 @@ void PPCAsmPrinter::EmitInstruction(cons
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymGotTlsGD = MCSymbolRefExpr::create(
- MOSymbol, Subtarget->isPPC64() ? MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO
- : MCSymbolRefExpr::VK_PPC_GOT_TLSGD,
+ MOSymbol, IsPPC64 ? MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO
+ : MCSymbolRefExpr::VK_PPC_GOT_TLSGD,
OutContext);
EmitToStreamer(*OutStreamer,
- MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDI8 : PPC::ADDI)
+ MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymGotTlsGD));
@@ -1046,7 +1044,7 @@ void PPCAsmPrinter::EmitInstruction(cons
case PPC::ADDIStlsldHA: {
// Transform: %xd = ADDIStlsldHA %x2, @sym
// Into: %xd = ADDIS8 %x2, sym at got@tlsld at ha
- assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
+ assert(IsPPC64 && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -1069,11 +1067,11 @@ void PPCAsmPrinter::EmitInstruction(cons
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymGotTlsLD = MCSymbolRefExpr::create(
- MOSymbol, Subtarget->isPPC64() ? MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO
- : MCSymbolRefExpr::VK_PPC_GOT_TLSLD,
+ MOSymbol, IsPPC64 ? MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO
+ : MCSymbolRefExpr::VK_PPC_GOT_TLSLD,
OutContext);
EmitToStreamer(*OutStreamer,
- MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDI8 : PPC::ADDI)
+ MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymGotTlsLD));
@@ -1102,7 +1100,7 @@ void PPCAsmPrinter::EmitInstruction(cons
OutContext);
EmitToStreamer(
*OutStreamer,
- MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDIS8 : PPC::ADDIS)
+ MCInstBuilder(IsPPC64 ? PPC::ADDIS8 : PPC::ADDIS)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymDtprel));
@@ -1121,7 +1119,7 @@ void PPCAsmPrinter::EmitInstruction(cons
MCSymbolRefExpr::create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_LO,
OutContext);
EmitToStreamer(*OutStreamer,
- MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDI8 : PPC::ADDI)
+ MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymDtprel));
@@ -1168,7 +1166,7 @@ void PPCAsmPrinter::EmitInstruction(cons
// suite shows a handful of test cases that fail this check for
// Darwin. Those need to be investigated before this sanity test
// can be enabled for those subtargets.
- if (!Subtarget->isDarwin()) {
+ if (!IsDarwin) {
unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
const MachineOperand &MO = MI->getOperand(OpNum);
if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
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