[llvm] r375414 - [ARM] Extra qdadd patterns
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 21 07:06:49 PDT 2019
Author: dmgreen
Date: Mon Oct 21 07:06:49 2019
New Revision: 375414
URL: http://llvm.org/viewvc/llvm-project?rev=375414&view=rev
Log:
[ARM] Extra qdadd patterns
This adds some new qdadd patterns to go along with the other recently added
qadd's.
Differential Revision: https://reviews.llvm.org/D68999
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/test/CodeGen/ARM/qdadd.ll
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=375414&r1=375413&r2=375414&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Oct 21 07:06:49 2019
@@ -3759,6 +3759,10 @@ def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b
(QADD GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b),
(QSUB GPR:$a, GPR:$b)>;
+def : ARMV5TEPat<(saddsat(saddsat rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
+ (QDADD rGPR:$Rm, rGPR:$Rn)>;
+def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
+ (QDSUB rGPR:$Rm, rGPR:$Rn)>;
def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
(QADD8 rGPR:$Rm, rGPR:$Rn)>;
def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=375414&r1=375413&r2=375414&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 21 07:06:49 2019
@@ -2399,6 +2399,10 @@ def : Thumb2DSPPat<(saddsat rGPR:$Rm, rG
(t2QADD rGPR:$Rm, rGPR:$Rn)>;
def : Thumb2DSPPat<(ssubsat rGPR:$Rm, rGPR:$Rn),
(t2QSUB rGPR:$Rm, rGPR:$Rn)>;
+def : Thumb2DSPPat<(saddsat(saddsat rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
+ (t2QDADD rGPR:$Rm, rGPR:$Rn)>;
+def : Thumb2DSPPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
+ (t2QDSUB rGPR:$Rm, rGPR:$Rn)>;
def : Thumb2DSPPat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
(t2QADD8 rGPR:$Rm, rGPR:$Rn)>;
def : Thumb2DSPPat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
Modified: llvm/trunk/test/CodeGen/ARM/qdadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/qdadd.ll?rev=375414&r1=375413&r2=375414&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/qdadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/qdadd.ll Mon Oct 21 07:06:49 2019
@@ -36,14 +36,12 @@ define i32 @qdadd(i32 %x, i32 %y) nounwi
;
; CHECK-T2DSP-LABEL: qdadd:
; CHECK-T2DSP: @ %bb.0:
-; CHECK-T2DSP-NEXT: qadd r0, r0, r0
-; CHECK-T2DSP-NEXT: qadd r0, r0, r1
+; CHECK-T2DSP-NEXT: qdadd r0, r0, r1
; CHECK-T2DSP-NEXT: bx lr
;
; CHECK-ARM-LABEL: qdadd:
; CHECK-ARM: @ %bb.0:
-; CHECK-ARM-NEXT: qadd r0, r0, r0
-; CHECK-ARM-NEXT: qadd r0, r0, r1
+; CHECK-ARM-NEXT: qdadd r0, r0, r1
; CHECK-ARM-NEXT: bx lr
%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
%tmp = call i32 @llvm.sadd.sat.i32(i32 %z, i32 %y)
@@ -82,14 +80,12 @@ define i32 @qdadd_c(i32 %x, i32 %y) noun
;
; CHECK-T2DSP-LABEL: qdadd_c:
; CHECK-T2DSP: @ %bb.0:
-; CHECK-T2DSP-NEXT: qadd r0, r0, r0
-; CHECK-T2DSP-NEXT: qadd r0, r1, r0
+; CHECK-T2DSP-NEXT: qdadd r0, r0, r1
; CHECK-T2DSP-NEXT: bx lr
;
; CHECK-ARM-LABEL: qdadd_c:
; CHECK-ARM: @ %bb.0:
-; CHECK-ARM-NEXT: qadd r0, r0, r0
-; CHECK-ARM-NEXT: qadd r0, r1, r0
+; CHECK-ARM-NEXT: qdadd r0, r0, r1
; CHECK-ARM-NEXT: bx lr
%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
%tmp = call i32 @llvm.sadd.sat.i32(i32 %y, i32 %z)
@@ -128,14 +124,12 @@ define i32 @qdsub(i32 %x, i32 %y) nounwi
;
; CHECK-T2DSP-LABEL: qdsub:
; CHECK-T2DSP: @ %bb.0:
-; CHECK-T2DSP-NEXT: qadd r0, r0, r0
-; CHECK-T2DSP-NEXT: qsub r0, r1, r0
+; CHECK-T2DSP-NEXT: qdsub r0, r1, r0
; CHECK-T2DSP-NEXT: bx lr
;
; CHECK-ARM-LABEL: qdsub:
; CHECK-ARM: @ %bb.0:
-; CHECK-ARM-NEXT: qadd r0, r0, r0
-; CHECK-ARM-NEXT: qsub r0, r1, r0
+; CHECK-ARM-NEXT: qdsub r0, r1, r0
; CHECK-ARM-NEXT: bx lr
%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
%tmp = call i32 @llvm.ssub.sat.i32(i32 %y, i32 %z)
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