[PATCH] D69249: [Alignment] Change implementation of TargetCallingConv::OrigAlign

[Guillaume Chatelet via Phabricator via llvm-commits]

gchatelet added a comment.

It is possible that the current implementation reserves the zero value as an error, although it is currently not checked.
Maybe it is illegal to call `getOrigAlign` before `setOrigAlign`?

If this is the intended behavior then some code is broken, adding an `assert(A && "OrigAlign must be set");` in `getOrigAlign`makes the following tests fail:

  LLVM :: CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll
  LLVM :: CodeGen/ARM/GlobalISel/arm-unsupported.ll
  LLVM :: CodeGen/ARM/arm-vld1.ll
  LLVM :: CodeGen/ARM/arm-vlddup.ll
  LLVM :: CodeGen/ARM/fp16-instructions.ll
  LLVM :: CodeGen/ARM/fp16-no-condition.ll
  LLVM :: CodeGen/ARM/fp16-vminmaxnm-safe.ll
  LLVM :: CodeGen/ARM/fp16-vminmaxnm.ll
  LLVM :: CodeGen/ARM/inc-of-add.ll
  LLVM :: CodeGen/ARM/sub-of-not.ll
  LLVM :: CodeGen/ARM/swift-return.ll
  LLVM :: CodeGen/ARM/umulo-128-legalisation-lowering.ll
  LLVM :: CodeGen/ARM/vld-vst-upgrade.ll
  LLVM :: CodeGen/ARM/vldm-sched-a9.ll
  LLVM :: CodeGen/ARM/vtrn.ll
  LLVM :: CodeGen/ARM/vuzp.ll
  LLVM :: CodeGen/ARM/vzip.ll
  LLVM :: CodeGen/Mips/cconv/pr33883.ll
  LLVM :: CodeGen/Mips/cconv/return-struct.ll
  LLVM :: CodeGen/Mips/cconv/vector.ll
  LLVM :: CodeGen/Mips/fp16-promote.ll
  LLVM :: CodeGen/Mips/return-vector.ll
  LLVM :: CodeGen/Thumb/umulo-128-legalisation-lowering.ll
  LLVM :: CodeGen/Thumb2/mve-shuffle.ll
  LLVM :: CodeGen/Thumb2/umulo-128-legalisation-lowering.ll


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69249/new/

https://reviews.llvm.org/D69249