[PATCH] D69212: [RISCV] Sign-extend 32-bit integer inline assembly operands on RV64I

[James Clarke via Phabricator via llvm-commits]

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GCC forces its in-register representation of 32-bit integers to be
sign-extended (ignoring whether it was a signed type in the source),
which gets exposed to inline assembly, commonly due to comparisons
against other sign-extended registers written to in the assembly, such
as in FreeBSD's atomic.h.

Since i32 is not legal for RV64I, we end up with a zero extension
(presumably because isZExtFree returns true and is preferred) for i32
loads consumed by inline assembly, deviating from GCC's exposed
behaviour. 64-bit MIPS (for which GCC also has the same in-register
representation of 32-bit integers) does not suffer from this bug because
it has a GPR32 register class and can use a normal non-extending load
(which is by default the sign-extending variant).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69212

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
  llvm/test/CodeGen/RISCV/inline-asm.ll

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