[PATCH] D69232: [PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: jsji, nemanjai, hfinkel, PowerPC.
Herald added subscribers: shchenz, wuzish, MaskRay, kbarton, hiraditya.
Herald added a project: LLVM.

If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling.

  // The mayLoad and mayStore flags default to false.
  // Conservatively assume hasSideEffects if it wasn't explicit.
  if (InstInfo->hasSideEffects_Unset)
    InstInfo->hasSideEffects = true;

PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions.


https://reviews.llvm.org/D69232

Files:
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/extract-and-store.ll
  llvm/test/CodeGen/PowerPC/mi-scheduling.ll

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