[llvm] r375367 - AMDGPU: Increase vcc liveness scan threshold
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 20 10:44:17 PDT 2019
Author: arsenm
Date: Sun Oct 20 10:44:17 2019
New Revision: 375367
URL: http://llvm.org/viewvc/llvm-project?rev=375367&view=rev
Log:
AMDGPU: Increase vcc liveness scan threshold
Avoids a test regression in a future patch. Also add debug printing on
this case, so I waste less time debugging folds in the future.
Modified:
llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll
llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
llvm/trunk/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
llvm/trunk/test/CodeGen/AMDGPU/fence-barrier.ll
llvm/trunk/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp?rev=375367&r1=375366&r2=375367&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp Sun Oct 20 10:44:17 2019
@@ -239,9 +239,11 @@ static bool updateOperand(FoldCandidate
if ((Fold.isImm() || Fold.isFI() || Fold.isGlobal()) && Fold.needsShrink()) {
MachineBasicBlock *MBB = MI->getParent();
- auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI);
- if (Liveness != MachineBasicBlock::LQR_Dead)
+ auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI, 16);
+ if (Liveness != MachineBasicBlock::LQR_Dead) {
+ LLVM_DEBUG(dbgs() << "Not shrinking " << MI << " due to vcc liveness\n");
return false;
+ }
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
int Op32 = Fold.getShrinkOpcode();
Modified: llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll?rev=375367&r1=375366&r2=375367&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll Sun Oct 20 10:44:17 2019
@@ -245,7 +245,6 @@ define amdgpu_kernel void @test_copy_v4i
; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: s_movk_i32 s1, 0xff
-; SI-NEXT: s_movk_i32 s2, 0x900
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -257,7 +256,7 @@ define amdgpu_kernel void @test_copy_v4i
; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_and_b32_e32 v1, s1, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -326,7 +325,6 @@ define amdgpu_kernel void @test_copy_v4i
; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
; SI-NEXT: s_mov_b32 s16, 0xff00
; SI-NEXT: s_movk_i32 s17, 0xff
-; SI-NEXT: s_movk_i32 s18, 0x900
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s8, s4
; SI-NEXT: s_mov_b32 s9, s5
@@ -345,7 +343,7 @@ define amdgpu_kernel void @test_copy_v4i
; SI-NEXT: v_and_b32_e32 v3, s17, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v1, s17, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s18, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x900, v2
; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
Modified: llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll?rev=375367&r1=375366&r2=375367&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll Sun Oct 20 10:44:17 2019
@@ -280,7 +280,6 @@ define amdgpu_kernel void @load_v4i8_to_
; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; SI-NEXT: s_movk_i32 s13, 0x900
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; SI-NEXT: v_add_i32_e32 v7, vcc, 9, v1
@@ -298,7 +297,7 @@ define amdgpu_kernel void @load_v4i8_to_
; SI-NEXT: v_or_b32_e32 v0, v6, v7
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; SI-NEXT: v_and_b32_e32 v1, s12, v4
-; SI-NEXT: v_add_i32_e32 v0, vcc, s13, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0
; SI-NEXT: v_or_b32_e32 v1, v5, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
Modified: llvm/trunk/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll?rev=375367&r1=375366&r2=375367&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll Sun Oct 20 10:44:17 2019
@@ -7,8 +7,6 @@ declare void @llvm.amdgcn.s.barrier() #1
; Function Attrs: nounwind
; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop:
-; SI: s_movk_i32 [[K_0X88:s[0-9]+]], 0x
-; SI: s_movk_i32 [[K_0X100:s[0-9]+]], 0x100
; CHECK: BB0_1:
; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]],
; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]]
@@ -16,9 +14,9 @@ declare void @llvm.amdgcn.s.barrier() #1
; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR8]]
; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], vcc, 0x80, [[VADDR]]
; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]]
-; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, [[K_0X88]], [[VADDR]]
+; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, 0x88, [[VADDR]]
; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x88]]
-; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, [[K_0X100]], [[VADDR]]
+; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, 0x100, [[VADDR]]
; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]]
; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:2
Modified: llvm/trunk/test/CodeGen/AMDGPU/fence-barrier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fence-barrier.ll?rev=375367&r1=375366&r2=375367&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fence-barrier.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fence-barrier.ll Sun Oct 20 10:44:17 2019
@@ -54,8 +54,7 @@ define amdgpu_kernel void @test_local(i3
}
; GCN-LABEL: {{^}}test_global
-; GCN: s_movk_i32 [[K:s[0-9]+]], 0x888
-; GCN: v_add_u32_e32 v{{[0-9]+}}, vcc, [[K]], v{{[0-9]+}}
+; GCN: v_add_u32_e32 v{{[0-9]+}}, vcc, 0x888, v{{[0-9]+}}
; GCN: flat_store_dword
; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GCN-NEXT: s_barrier
Modified: llvm/trunk/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll?rev=375367&r1=375366&r2=375367&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll Sun Oct 20 10:44:17 2019
@@ -80,10 +80,10 @@ define hidden amdgpu_kernel void @clmem_
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
-; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
-; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
+; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
+; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
More information about the llvm-commits
mailing list