[PATCH] D66088: AMD Znver2 (Rome) Scheduler enablement

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ScheduleZnver2.td:90-91
+
+// 5 Cycles load-to use Latency is captured
+def : ReadAdvance<ReadAfterLd, 5>;
+
----------------
But `let LoadLatency = 4;`.
Shouldn't this also be `4`?


================
Comment at: llvm/lib/Target/X86/X86ScheduleZnver2.td:155
+                          int Lat, list<int> Res = [], int UOps = 1,
+                          int LoadLat = 7, int LoadUOps = 0> {
+  // Register variant takes 1-cycle on Execution Port.
----------------
But `ReadAdvance<ReadAfterVecLd` is at `7`?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66088/new/

https://reviews.llvm.org/D66088