[PATCH] D69185: [AArch64] Output the pseudo SPACE in asm and object files

[Momchil Velikov via Phabricator via llvm-commits]

chill created this revision.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.
chill added a child revision: D69118: [AArch64] Move the branch relaxation pass after BTI insertion.
chill added reviewers: t.p.northover, ostannard.

It outputs nothing, but is useful for writing tests, checking asm output.


https://reviews.llvm.org/D69185

Files:
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
  llvm/test/CodeGen/AArch64/space.ll


Index: llvm/test/CodeGen/AArch64/space.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/space.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple aarch64               %s -o - | FileCheck %s
+; RUN: llc -mtriple aarch64 -filetype=obj %s -o - | llvm-objdump --arch=aarch64  -d - | FileCheck %s --check-prefix=DUMP
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+
+define dso_local void @f(i64 %v) {
+entry:
+  %dummy = tail call i64 @llvm.aarch64.space(i32 32684, i64 %v)
+  ret void
+}
+; CHECK: // SPACE
+; CHECK-NEXT: ret
+; DUMP-LABEL: f:
+; DUMP-NEXT: ret
+
+declare dso_local i64 @llvm.aarch64.space(i32, i64) local_unnamed_addr #0
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -601,8 +601,9 @@
     MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
     Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
     return;
-  } else if (MI.getOpcode() == AArch64::CompilerBarrier) {
-    // This just prevents the compiler from reordering accesses, no actual code.
+  } else if (MI.getOpcode() == AArch64::CompilerBarrier || MI.getOpcode() == AArch64::SPACE) {
+    // CompilerBarrier just prevents the compiler from reordering accesses, and
+    // SPACE just increases basic block size, in both cases no actual code.
     return;
   }
 
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
===================================================================
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -282,6 +282,12 @@
     return;
   }
 
+  if (Opcode == AArch64::SPACE) {
+    O << '\t' << MAI.getCommentString() << " SPACE";
+    printAnnotation(O, Annot);
+    return;
+  }
+
   // Instruction TSB is specified as a one operand instruction, but 'csync' is
   // not encoded, so for printing it is treated as a special case here:
   if (Opcode == AArch64::TSB) {


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