[PATCH] D69172: AMDGPU: Fix SMEM WAR hazard for gfx10 readlane

Fri Oct 18 10:48:51 PDT 2019

arsenm added a comment.

In D69172#1714838 <https://reviews.llvm.org/D69172#1714838>, @arsenm wrote:

> In D69172#1714808 <https://reviews.llvm.org/D69172#1714808>, @rampitec wrote:
>
> > It is OK as a w/a, but real opcode should not appear that early.
> >  @arsenm What is the reason to use MC opcode in the SIFrameLowering::emitEpilogue()?
> >
> >   BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
> >           FuncInfo->getFrameOffsetReg())
> >   
> >   
>
>
> There is a reason for it, but I don't remember what it is. I've tried to fix this multiple times in the past, and then rediscovered why. I think it had something to do with an operand constraint/encoding change in VI

The same is also done in spillSGPR/restoreSGPR, the PEI version was just reproducing the same

Repository:
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  https://reviews.llvm.org/D69172/new/

https://reviews.llvm.org/D69172