[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[James Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

I wonder whether, instead of putting all the scheduling resource information as part of the instruction definition, we should be doing something like we do with patterns, ie declaring them separately (either in each RISCVInstrInfoX.td, or in RISCVSchedule.td to keep scheduling completely separate from encoding and codegen). For example (formatting aside):

  def : InstRW<[WriteFALU32], (instrs FADD_S, FSUB_S, FSGNJ_S, FSGNJN_S, FSGNJX_S, FMIN_S, FMAX_S)>;


Repository:
  rL LLVM

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  https://reviews.llvm.org/D68685/new/

https://reviews.llvm.org/D68685