[llvm] r375233 - Revert r375152 as it is causing failures on EXPENSIVE_CHECKS bot
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 18 06:38:47 PDT 2019
Author: nemanjai
Date: Fri Oct 18 06:38:46 2019
New Revision: 375233
URL: http://llvm.org/viewvc/llvm-project?rev=375233&view=rev
Log:
Revert r375152 as it is causing failures on EXPENSIVE_CHECKS bot
Modified:
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
llvm/trunk/test/CodeGen/PowerPC/brcond.ll
llvm/trunk/test/CodeGen/PowerPC/pr42492.ll
llvm/trunk/test/CodeGen/PowerPC/tocSaveInPrologue.ll
llvm/trunk/test/CodeGen/PowerPC/vec-min-max.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=375233&r1=375232&r2=375233&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Fri Oct 18 06:38:46 2019
@@ -93,7 +93,7 @@ EnableMachineCombinerPass("ppc-machine-c
static cl::opt<bool>
ReduceCRLogical("ppc-reduce-cr-logicals",
cl::desc("Expand eligible cr-logical binary ops to branches"),
- cl::init(true), cl::Hidden);
+ cl::init(false), cl::Hidden);
extern "C" void LLVMInitializePowerPCTarget() {
// Register the targets
RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
Modified: llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll?rev=375233&r1=375232&r2=375233&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll Fri Oct 18 06:38:46 2019
@@ -36,7 +36,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, 0
-; CHECK-NEXT: b .LBB0_17
+; CHECK-NEXT: b .LBB0_16
; CHECK-NEXT: .LBB0_2: # %bb1
; CHECK-NEXT: lfd 0, 400(1)
; CHECK-NEXT: lis 3, 15856
@@ -166,11 +166,13 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: bl __gcc_qsub at PLT
; CHECK-NEXT: stfd 2, 176(1)
; CHECK-NEXT: stfd 1, 168(1)
-; CHECK-NEXT: fcmpu 1, 2, 27
+; CHECK-NEXT: fcmpu 0, 2, 27
; CHECK-NEXT: lwz 3, 180(1)
-; CHECK-NEXT: fcmpu 0, 1, 27
-; CHECK-NEXT: crandc 20, 2, 4
+; CHECK-NEXT: fcmpu 1, 1, 27
+; CHECK-NEXT: crandc 20, 6, 0
+; CHECK-NEXT: cror 21, 5, 7
; CHECK-NEXT: stw 3, 268(1)
+; CHECK-NEXT: cror 20, 21, 20
; CHECK-NEXT: lwz 3, 176(1)
; CHECK-NEXT: stw 3, 264(1)
; CHECK-NEXT: lwz 3, 172(1)
@@ -179,11 +181,8 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: lwz 3, 168(1)
; CHECK-NEXT: stw 3, 272(1)
; CHECK-NEXT: lfd 31, 272(1)
-; CHECK-NEXT: bc 12, 20, .LBB0_14
-; CHECK-NEXT: # %bb.10: # %bb1
-; CHECK-NEXT: cror 20, 1, 3
-; CHECK-NEXT: bc 12, 20, .LBB0_14
-; CHECK-NEXT: # %bb.11: # %bb2
+; CHECK-NEXT: bc 12, 20, .LBB0_13
+; CHECK-NEXT: # %bb.10: # %bb2
; CHECK-NEXT: fneg 28, 31
; CHECK-NEXT: stfd 28, 48(1)
; CHECK-NEXT: lis 3, 16864
@@ -232,15 +231,15 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: crandc 20, 6, 1
; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: addis 3, 3, -32768
-; CHECK-NEXT: bc 12, 20, .LBB0_13
-; CHECK-NEXT: # %bb.12: # %bb2
+; CHECK-NEXT: bc 12, 20, .LBB0_12
+; CHECK-NEXT: # %bb.11: # %bb2
; CHECK-NEXT: ori 3, 4, 0
-; CHECK-NEXT: b .LBB0_13
-; CHECK-NEXT: .LBB0_13: # %bb2
+; CHECK-NEXT: b .LBB0_12
+; CHECK-NEXT: .LBB0_12: # %bb2
; CHECK-NEXT: subfic 4, 3, 0
; CHECK-NEXT: subfe 3, 29, 30
-; CHECK-NEXT: b .LBB0_17
-; CHECK-NEXT: .LBB0_14: # %bb3
+; CHECK-NEXT: b .LBB0_16
+; CHECK-NEXT: .LBB0_13: # %bb3
; CHECK-NEXT: stfd 31, 112(1)
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: stw 3, 148(1)
@@ -287,13 +286,13 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: crandc 20, 6, 0
; CHECK-NEXT: cror 20, 5, 20
; CHECK-NEXT: addis 3, 3, -32768
-; CHECK-NEXT: bc 12, 20, .LBB0_15
-; CHECK-NEXT: b .LBB0_16
-; CHECK-NEXT: .LBB0_15: # %bb3
+; CHECK-NEXT: bc 12, 20, .LBB0_14
+; CHECK-NEXT: b .LBB0_15
+; CHECK-NEXT: .LBB0_14: # %bb3
; CHECK-NEXT: addi 4, 3, 0
-; CHECK-NEXT: .LBB0_16: # %bb3
+; CHECK-NEXT: .LBB0_15: # %bb3
; CHECK-NEXT: mr 3, 30
-; CHECK-NEXT: .LBB0_17: # %bb5
+; CHECK-NEXT: .LBB0_16: # %bb5
; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
Modified: llvm/trunk/test/CodeGen/PowerPC/brcond.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/brcond.ll?rev=375233&r1=375232&r2=375233&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/brcond.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/brcond.ll Fri Oct 18 06:38:46 2019
@@ -1,7 +1,5 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
-; RUN: -ppc-reduce-cr-logicals=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
-; RUN: -ppc-reduce-cr-logicals=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
; CHECK-LABEL: testi32slt
Modified: llvm/trunk/test/CodeGen/PowerPC/pr42492.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr42492.ll?rev=375233&r1=375232&r2=375233&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr42492.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/pr42492.ll Fri Oct 18 06:38:46 2019
@@ -4,27 +4,13 @@
define void @f(i8*, i8*, i64*) {
; Check we don't assert and this is not a Hardware Loop
; CHECK-LABEL: f:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpld 3, 4
-; CHECK-NEXT: beqlr 0
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: ld 6, 8(5)
-; CHECK-NEXT: not 3, 3
-; CHECK-NEXT: add 3, 3, 4
-; CHECK-NEXT: li 4, 0
-; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: .LBB0_2: #
-; CHECK-NEXT: sldi 6, 6, 4
-; CHECK-NEXT: cmplwi 4, 14
-; CHECK-NEXT: addi 7, 4, 1
-; CHECK-NEXT: bc 12, 1, .LBB0_4
-; CHECK-NEXT: # %bb.3: #
-; CHECK-NEXT: cmpd 3, 4
-; CHECK-NEXT: mr 4, 7
-; CHECK-NEXT: bc 4, 2, .LBB0_2
-; CHECK-NEXT: .LBB0_4:
-; CHECK-NEXT: std 6, 8(5)
-; CHECK-NEXT: blr
+; CHECK: .LBB0_2: #
+; CHECK-NEXT: cmplwi
+; CHECK-NEXT: cmpd
+; CHECK-NEXT: sldi
+; CHECK-NEXT: cror
+; CHECK-NEXT: addi
+; CHECK-NEXT: bc
%4 = icmp eq i8* %0, %1
br i1 %4, label %9, label %5
Modified: llvm/trunk/test/CodeGen/PowerPC/tocSaveInPrologue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tocSaveInPrologue.ll?rev=375233&r1=375232&r2=375233&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tocSaveInPrologue.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tocSaveInPrologue.ll Fri Oct 18 06:38:46 2019
@@ -16,17 +16,16 @@ define dso_local void @test(void (i32)*
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: mr r29, r5
+; CHECK-NEXT: cmpwi cr1, r4, 11
; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: extsw r28, r4
; CHECK-NEXT: std r2, 24(r1)
; CHECK-NEXT: cmpwi r29, 1
-; CHECK-NEXT: bc 12, lt, .LBB0_3
-; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: cmpwi cr0, r4, 11
-; CHECK-NEXT: bc 12, lt, .LBB0_3
+; CHECK-NEXT: cror 4*cr5+lt, lt, 4*cr1+lt
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_2
; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: .LBB0_2: # %for.body.us
-; CHECK-NEXT: #
+; CHECK-NEXT: .LBB0_1: # %for.body.us
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: mtctr r30
; CHECK-NEXT: mr r3, r28
; CHECK-NEXT: mr r12, r30
@@ -34,8 +33,8 @@ define dso_local void @test(void (i32)*
; CHECK-NEXT: ld 2, 24(r1)
; CHECK-NEXT: addi r29, r29, -1
; CHECK-NEXT: cmplwi r29, 0
-; CHECK-NEXT: bne cr0, .LBB0_2
-; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
+; CHECK-NEXT: bne cr0, .LBB0_1
+; CHECK-NEXT: .LBB0_2: # %for.cond.cleanup
; CHECK-NEXT: mtctr r30
; CHECK-NEXT: mr r3, r28
; CHECK-NEXT: mr r12, r30
Modified: llvm/trunk/test/CodeGen/PowerPC/vec-min-max.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec-min-max.ll?rev=375233&r1=375232&r2=375233&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec-min-max.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec-min-max.ll Fri Oct 18 06:38:46 2019
@@ -240,23 +240,22 @@ entry:
define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
; CHECK-LABEL: invalidv1i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: mfvsrd 3, 36
; CHECK-NEXT: xxswapd 0, 36
-; CHECK-NEXT: mfvsrd 4, 34
-; CHECK-NEXT: xxswapd 1, 34
-; CHECK-NEXT: cmpld 4, 3
-; CHECK-NEXT: cmpd 1, 4, 3
+; CHECK-NEXT: mfvsrd 4, 36
+; CHECK-NEXT: mfvsrd 5, 34
; CHECK-NEXT: mfvsrd 3, 0
+; CHECK-NEXT: xxswapd 0, 34
+; CHECK-NEXT: cmpld 5, 4
+; CHECK-NEXT: cmpd 1, 5, 4
; CHECK-NEXT: crandc 20, 4, 2
-; CHECK-NEXT: mfvsrd 4, 1
-; CHECK-NEXT: cmpld 1, 4, 3
-; CHECK-NEXT: bc 12, 20, .LBB12_3
+; CHECK-NEXT: mfvsrd 6, 0
+; CHECK-NEXT: cmpld 1, 6, 3
+; CHECK-NEXT: crand 21, 2, 4
+; CHECK-NEXT: cror 20, 21, 20
+; CHECK-NEXT: bc 12, 20, .LBB12_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: crand 20, 2, 4
-; CHECK-NEXT: bc 12, 20, .LBB12_3
-; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: vmr 2, 4
-; CHECK-NEXT: .LBB12_3:
+; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: mfvsrd 4, 34
; CHECK-NEXT: mfvsrd 3, 0
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