[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Ana Pazos via Phabricator via llvm-commits]

apazos added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket32.td:16
+// This works with MachineScheduler. See MCSchedule.h for details.
+
+// Rocket machine model for scheduling and other instruction cost heuristics.
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Can you add to the comments a link to the processor model documentation used in the schedule definitions (latencies, function units types, etc.)?

Have you been able to run utils/schedcover.py on Rocket32Model and Rocket64Model?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68685/new/

https://reviews.llvm.org/D68685