[PATCH] D68232: [DAGCombine] Match a greater range of rotate when not all bits are demanded.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri requested changes to this revision.
lebedev.ri added inline comments.
This revision now requires changes to proceed.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6226
+    uint64_t RotAmount =
+        (LHS->getAPIntValue() + RHS->getAPIntValue()).getZExtValue();
+    // For vectors, only allow exact match.
----------------
Use `getLimitedValue()`


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6230-6235
+    // For scalar, check that the type we use for rotation cover all demanded
+    // bits and is legal.
+    APInt RotMask =
+        APInt::getMaxValue(RotAmount).zextOrTrunc(DemandedBits.getBitWidth());
+    if (!DemandedBits.isSubsetOf(RotMask))
+      return false;
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I don't understand the logic here.
This might need some comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6233
+    APInt RotMask =
+        APInt::getMaxValue(RotAmount).zextOrTrunc(DemandedBits.getBitWidth());
+    if (!DemandedBits.isSubsetOf(RotMask))
----------------
Should this use `getAllOnesValue()` directly?


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6240-6243
+    HasROTL = hasOperation(ISD::ROTL, RotVT);
+    HasROTR = hasOperation(ISD::ROTR, RotVT);
+    if (!HasROTL && !HasROTR)
+      return SDValue();
----------------
Precommit.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68232/new/

https://reviews.llvm.org/D68232