[PATCH] D67158: [ARM] Begin adding IR intrinsics for MVE instructions.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham added a comment.

Oh, nearly forgot: I renamed the `vcvt` intrinsic again, to put "narrow" back into the name (it's now `vcvt_narrow`).

Rationale: the MVE VCVT instructions can't all be treated exactly the same way by their IR intrinsics, because conversions to a narrower element type need an extra input parameter giving the previous value of their output register, which they only overwrite half of. Non-narrowing VCVTs will have a simpler type signature without that parameter.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67158/new/

https://reviews.llvm.org/D67158