[PATCH] D67392: [ARM][ParallelDSP] Change smlad insertion order

[Sam Parker via Phabricator via llvm-commits]

samparker marked 2 inline comments as done.
samparker added inline comments.


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Comment at: lib/Target/ARM/ARMParallelDSP.cpp:379
+  for (auto Write : Writes) {
+    for (auto Read : Loads) {
       MemoryLocation ReadLoc =
----------------
SjoerdMeijer wrote:
> Just curious, why did you change the iteration order, Loads/Writes vs. Writes/Loads? 
We know that Loads isn't empty, but Writes maybe so we can skip the loop if it is.


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Comment at: test/CodeGen/ARM/ParallelDSP/blocks.ll:139
+; scalars.
+; CHECK-LABEL: num_load_limit
+; CHECK: call i32 @llvm.arm.smlad
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SjoerdMeijer wrote:
> Double checking I understand this test: this test has 16 loads, so is within the limit of 16.
> So why don't we generate the 4th SMLAD?
We're within the limit, but it looks like there's some limitation with the search algorithm... the adds are just ordered differently to 'usual'.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67392/new/

https://reviews.llvm.org/D67392