[PATCH] D68828: [AMDGPU] Allow DPP combiner to work with REG_SEQUENCE

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:539-543
+      for (unsigned I = 1, E = S->getNumOperands(); I < E; I += 2) {
+        MachineOperand &Op = S->getOperand(I);
+        if (!MRI->getVRegDef(Op.getReg()))
+          Op.setIsUndef(true);
+      }
----------------
rampitec wrote:
> arsenm wrote:
> > This seems like a questionable way to preserve undefs. Can you avoid doing this by checking getVRegDef?
> What's wrong with it? A register either has def or not. The other way would be to keep all reg_sequences along with the info about all subregs, if they were combined or not.
What if the instruction were incorrectly erased? The undef flag would have been present and this would no longer catch it


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68828/new/

https://reviews.llvm.org/D68828