[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Javed Absar via Phabricator via llvm-commits]

javed.absar added a comment.

In D68685#1705570 <https://reviews.llvm.org/D68685#1705570>, @rogfer01 wrote:

> @javedabsar (or @javed.absar) I seem to recall you have experience with schedulers. If you could give us a hand here that'd be great! :)


Sure no problem Roger :)

Could you please point me to some doc which describes the pipeline model of RISCVRocket64 - i.e. what kind of processing units are available, how each instruction flows through the pipeline (fully pipelined or partially, latencies, resource dependences)?

That would be my starting point to match against the schedules defined in schedule*.td.


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