[PATCH] D68550: [X86] Teach X86MCInstLower to swap operands of commutable instructions to enable 2-byte VEX encoding.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM with one minor query.



================
Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:915
+        MI->getOpcode() != X86::VMOVHLPSrr &&
+        MI->getOpcode() != X86::VUNPCKHPDrr) {
+      if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) &&
----------------
The need to exclude specific opcodes here is unfortunate - maybe add a comment explaining why? Maybe even put them under a separate 'no doing' case statement?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68550/new/

https://reviews.llvm.org/D68550