[llvm] r374641 - [mips] Rely on GPR size not ABI when select instruction to load value into register
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 12 00:42:51 PDT 2019
Author: atanasyan
Date: Sat Oct 12 00:42:51 2019
New Revision: 374641
URL: http://llvm.org/viewvc/llvm-project?rev=374641&view=rev
Log:
[mips] Rely on GPR size not ABI when select instruction to load value into register
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=374641&r1=374640&r2=374641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Sat Oct 12 00:42:51 2019
@@ -3396,7 +3396,7 @@ bool MipsAsmParser::expandLoadDoubleImmT
ImmOp64 = convertIntToDoubleImm(ImmOp64);
if (Lo_32(ImmOp64) == 0) {
- if (isABI_N32() || isABI_N64()) {
+ if (isGP64bit()) {
if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false,
IDLoc, Out, STI))
return true;
@@ -3435,14 +3435,10 @@ bool MipsAsmParser::expandLoadDoubleImmT
if (emitPartialAddress(TOut, IDLoc, Sym))
return true;
- if (isABI_N64())
- TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
- IDLoc, STI);
- else
- TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
- IDLoc, STI);
+ TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
+ MCOperand::createExpr(LoExpr), IDLoc, STI);
- if (isABI_N32() || isABI_N64())
+ if (isGP64bit())
TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);
else {
TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);
@@ -3473,7 +3469,7 @@ bool MipsAsmParser::expandLoadDoubleImmT
if ((Lo_32(ImmOp64) == 0) &&
!((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) {
- if (isABI_N32() || isABI_N64()) {
+ if (isGP64bit()) {
if (TmpReg != Mips::ZERO &&
loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
Out, STI))
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