[llvm] r374597 - [mips] Use less instruction to load zero into FPR by li.s / li.d pseudos
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 11 14:51:24 PDT 2019
Author: atanasyan
Date: Fri Oct 11 14:51:23 2019
New Revision: 374597
URL: http://llvm.org/viewvc/llvm-project?rev=374597&view=rev
Log:
[mips] Use less instruction to load zero into FPR by li.s / li.d pseudos
If `li.s` or `li.d` loads zero into a FPR, it's not necessary to load
zero into `at` GPR register and then move its value into a floating
point register. We can use as a source register the `zero / $0` one.
Differential Revision: https://reviews.llvm.org/D68777
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/test/MC/Mips/macro-li.d.s
llvm/trunk/test/MC/Mips/macro-li.s.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=374597&r1=374596&r2=374597&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Fri Oct 11 14:51:23 2019
@@ -3345,13 +3345,16 @@ bool MipsAsmParser::expandLoadSingleImmT
uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64);
- unsigned TmpReg = getATReg(IDLoc);
- if (!TmpReg)
- return true;
+ unsigned TmpReg = Mips::ZERO;
+ if (ImmOp32 != 0) {
+ TmpReg = getATReg(IDLoc);
+ if (!TmpReg)
+ return true;
+ }
if (Lo_32(ImmOp64) == 0) {
- if (loadImmediate(ImmOp32, TmpReg, Mips::NoRegister, true, true, IDLoc, Out,
- STI))
+ if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister,
+ true, false, IDLoc, Out, STI))
return true;
TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
return false;
@@ -3469,24 +3472,26 @@ bool MipsAsmParser::expandLoadDoubleImmT
uint32_t LoImmOp64 = Lo_32(ImmOp64);
uint32_t HiImmOp64 = Hi_32(ImmOp64);
- unsigned TmpReg = getATReg(IDLoc);
- if (!TmpReg)
- return true;
+ unsigned TmpReg = Mips::ZERO;
+ if (ImmOp64 != 0) {
+ TmpReg = getATReg(IDLoc);
+ if (!TmpReg)
+ return true;
+ }
if ((LoImmOp64 == 0) &&
!((HiImmOp64 & 0xffff0000) && (HiImmOp64 & 0x0000ffff))) {
- // FIXME: In the case where the constant is zero, we can load the
- // register directly from the zero register.
-
if (isABI_N32() || isABI_N64()) {
- if (loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
+ if (TmpReg != Mips::ZERO &&
+ loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
Out, STI))
return true;
TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
return false;
}
- if (loadImmediate(HiImmOp64, TmpReg, Mips::NoRegister, true, false, IDLoc,
+ if (TmpReg != Mips::ZERO &&
+ loadImmediate(HiImmOp64, TmpReg, Mips::NoRegister, true, false, IDLoc,
Out, STI))
return true;
Modified: llvm/trunk/test/MC/Mips/macro-li.d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-li.d.s?rev=374597&r1=374596&r2=374597&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-li.d.s (original)
+++ llvm/trunk/test/MC/Mips/macro-li.d.s Fri Oct 11 14:51:23 2019
@@ -228,24 +228,18 @@ li.d $4, 12345678910123456789.1234567891
# N32-N64: ld $4, 0($1) # encoding: [0x00,0x00,0x24,0xdc]
li.d $f4, 0
-# O32: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
-# O32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44]
+# O32: mtc1 $zero, $f5 # encoding: [0x00,0x28,0x80,0x44]
# O32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44]
-# CHECK-MIPS32r2: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44]
-# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44]
-# N32-N64: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
-# N32-N64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44]
+# CHECK-MIPS32r2: mthc1 $zero, $f4 # encoding: [0x00,0x20,0xe0,0x44]
+# N32-N64: dmtc1 $zero, $f4 # encoding: [0x00,0x20,0xa0,0x44]
li.d $f4, 0.0
-# O32: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
-# O32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44]
+# O32: mtc1 $zero, $f5 # encoding: [0x00,0x28,0x80,0x44]
# O32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44]
-# CHECK-MIPS32r2: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44]
-# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44]
-# N32-N64: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
-# N32-N64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44]
+# CHECK-MIPS32r2: mthc1 $zero, $f4 # encoding: [0x00,0x20,0xe0,0x44]
+# N32-N64: dmtc1 $zero, $f4 # encoding: [0x00,0x20,0xa0,0x44]
li.d $f4, 1.12345
# ALL: .section .rodata,"a", at progbits
Modified: llvm/trunk/test/MC/Mips/macro-li.s.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-li.s.s?rev=374597&r1=374596&r2=374597&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-li.s.s (original)
+++ llvm/trunk/test/MC/Mips/macro-li.s.s Fri Oct 11 14:51:23 2019
@@ -45,12 +45,10 @@ li.s $4, 12345678910123456789.1234567891
# ALL: ori $4, $4, 21674 # encoding: [0xaa,0x54,0x84,0x34]
li.s $f4, 0
-# ALL: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
-# ALL: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44]
+# ALL: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44]
li.s $f4, 0.0
-# ALL: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
-# ALL: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44]
+# ALL: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44]
li.s $f4, 1.12345
# ALL: .section .rodata,"a", at progbits
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