[PATCH] D68341: [AIX] TOC pseudo expansion for 64bit large + 64bit small + 32bit large modes

[Hubert Tong via Phabricator via llvm-commits]

hubert.reinterpretcast added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll:23
+; LARGE:       lwz [[REG2:[0-9]+]], LC0 at l([[REG1]])
+; LARGE:       lwz [[REG3:[0-9]+]], 0([[REG2]])
+; LARGE:       addis [[REG4:[0-9]+]], LC1 at u(2)
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That the ordering and interleaving of the logical operations involved differ between the various cases seem to indicate that the test is already too complicated. Please reduce the test to use a single memory operand (e.g., store a constant or return the value read).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68341/new/

https://reviews.llvm.org/D68341