[PATCH] D68871: [X86][BtVer2] Improved latency and throughput of float/vector loads and stores.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, craig.topper, lebedev.ri.
Herald added subscribers: courbet, gbedwell.
andreadb added a comment.

F10225163: exegesis-report.txt <https://reviews.llvm.org/F10225163>

Posted the output from llvm-exegesis for all the affected instructions.


This patch introduces the following changes to the btver2 scheduling model:

The number of micro opcodes for YMM loads and stores is now 2 (it was incorrectly set to 1 for both aligned and misaligned loads/stores).

Increased the number of AGU resource cycles for YMM loads and stores to 2cy (instead of 1cy).

Removed JFPU01 and JFPX from the list of resources consumed by pure float/vector loads (no MMX).

I verified with llvm-exegesis that pure XMM/YMM loads are no-pipe. They are dispatched to the FPU but not really issues on JFPU01.


https://reviews.llvm.org/D68871

Files:
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s
  test/tools/llvm-mca/X86/BtVer2/load-store-alias.s
  test/tools/llvm-mca/X86/BtVer2/memcpy-like-test.s
  test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
  test/tools/llvm-mca/X86/BtVer2/resources-sse1.s
  test/tools/llvm-mca/X86/BtVer2/resources-sse2.s
  test/tools/llvm-mca/X86/BtVer2/resources-sse3.s

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