[llvm] r374561 - [AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write]_addtid_b32
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 11 07:53:26 PDT 2019
Author: dpreobra
Date: Fri Oct 11 07:53:26 2019
New Revision: 374561
URL: http://llvm.org/viewvc/llvm-project?rev=374561&view=rev
Log:
[AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write]_addtid_b32
See https://bugs.llvm.org/show_bug.cgi?id=37941
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D68787
Modified:
llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
llvm/trunk/test/MC/AMDGPU/ds-gfx9.s
llvm/trunk/test/MC/AMDGPU/gfx10_asm_all.s
llvm/trunk/test/MC/AMDGPU/gfx10_asm_err.s
llvm/trunk/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
Modified: llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/DSInstructions.td?rev=374561&r1=374560&r2=374561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/DSInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/DSInstructions.td Fri Oct 11 07:53:26 2019
@@ -81,6 +81,17 @@ class DS_Real <DS_Pseudo ds> :
// DS Pseudo instructions
+class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
+: DS_Pseudo<opName,
+ (outs),
+ (ins rc:$data0, offset:$offset, gds:$gds),
+ "$data0$offset$gds"> {
+
+ let has_addr = 0;
+ let has_data1 = 0;
+ let has_vdst = 0;
+}
+
class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
@@ -394,11 +405,12 @@ def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<
def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
}
+} // End has_m0_read = 0
+
let SubtargetPredicate = HasDSAddTid in {
-def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">;
+def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
}
-} // End has_m0_read = 0
} // End mayLoad = 0
defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">;
@@ -543,13 +555,14 @@ def DS_READ_I8_D16_HI : DS_1A_RET_Tied<
def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">;
def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
}
+} // End has_m0_read = 0
let SubtargetPredicate = HasDSAddTid in {
-def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">;
-}
-} // End has_m0_read = 0
+def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
}
+} // End mayStore = 0
+
def DS_CONSUME : DS_0A_RET<"ds_consume">;
def DS_APPEND : DS_0A_RET<"ds_append">;
def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
Modified: llvm/trunk/test/MC/AMDGPU/ds-gfx9.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/ds-gfx9.s?rev=374561&r1=374560&r2=374561&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/ds-gfx9.s (original)
+++ llvm/trunk/test/MC/AMDGPU/ds-gfx9.s Fri Oct 11 07:53:26 2019
@@ -33,10 +33,10 @@ ds_write_b16_d16_hi v8, v2
// VI-ERR: error: instruction not supported on this GPU
// GFX9: ds_write_b16_d16_hi v8, v2 ; encoding: [0x00,0x00,0xaa,0xd8,0x08,0x02,0x00,0x00]
-ds_write_addtid_b32 v8, v2
+ds_write_addtid_b32 v8
// VI-ERR: error: instruction not supported on this GPU
-// GFX9: ds_write_addtid_b32 v8, v2 ; encoding: [0x00,0x00,0x3a,0xd8,0x08,0x02,0x00,0x00]
+// GFX9: ds_write_addtid_b32 v8 ; encoding: [0x00,0x00,0x3a,0xd8,0x00,0x08,0x00,0x00]
-ds_read_addtid_b32 v8, v2
+ds_read_addtid_b32 v8
// VI-ERR: error: instruction not supported on this GPU
-// GFX9: ds_read_addtid_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd9,0x02,0x00,0x00,0x08]
+// GFX9: ds_read_addtid_b32 v8 ; encoding: [0x00,0x00,0x6c,0xd9,0x00,0x00,0x00,0x08]
Modified: llvm/trunk/test/MC/AMDGPU/gfx10_asm_all.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/gfx10_asm_all.s?rev=374561&r1=374560&r2=374561&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/gfx10_asm_all.s (original)
+++ llvm/trunk/test/MC/AMDGPU/gfx10_asm_all.s Fri Oct 11 07:53:26 2019
@@ -6538,47 +6538,47 @@ ds_read_u16_d16_hi v5, v1 offset:4
ds_read_u16_d16_hi v5, v1 offset:65535 gds
// GFX10: encoding: [0xff,0xff,0x9e,0xda,0x01,0x00,0x00,0x05]
-ds_write_addtid_b32 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x05,0x01,0x00,0x00]
+ds_write_addtid_b32 v5 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
-ds_write_addtid_b32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xda,0xff,0x01,0x00,0x00]
+ds_write_addtid_b32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0xff,0x00,0x00]
-ds_write_addtid_b32 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x05,0xff,0x00,0x00]
+ds_write_addtid_b32 v5 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
-ds_write_addtid_b32 v5, v1
-// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00]
+ds_write_addtid_b32 v5
+// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
-ds_write_addtid_b32 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00]
+ds_write_addtid_b32 v5 offset:0
+// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
-ds_write_addtid_b32 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xc0,0xda,0x05,0x01,0x00,0x00]
+ds_write_addtid_b32 v5 offset:4
+// GFX10: encoding: [0x04,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
-ds_write_addtid_b32 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xc2,0xda,0x05,0x01,0x00,0x00]
+ds_write_addtid_b32 v5 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xc2,0xda,0x00,0x05,0x00,0x00]
-ds_read_addtid_b32 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0x05]
+ds_read_addtid_b32 v5 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
-ds_read_addtid_b32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0xff]
+ds_read_addtid_b32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0xff]
-ds_read_addtid_b32 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xda,0xff,0x00,0x00,0x05]
+ds_read_addtid_b32 v5 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
-ds_read_addtid_b32 v5, v1
-// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05]
+ds_read_addtid_b32 v5
+// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
-ds_read_addtid_b32 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05]
+ds_read_addtid_b32 v5 offset:0
+// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
-ds_read_addtid_b32 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xc4,0xda,0x01,0x00,0x00,0x05]
+ds_read_addtid_b32 v5 offset:4
+// GFX10: encoding: [0x04,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
-ds_read_addtid_b32 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xc6,0xda,0x01,0x00,0x00,0x05]
+ds_read_addtid_b32 v5 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xc6,0xda,0x00,0x00,0x00,0x05]
ds_permute_b32 v0, v1, v2
// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0x02,0x00,0x00]
Modified: llvm/trunk/test/MC/AMDGPU/gfx10_asm_err.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/gfx10_asm_err.s?rev=374561&r1=374560&r2=374561&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/gfx10_asm_err.s (original)
+++ llvm/trunk/test/MC/AMDGPU/gfx10_asm_err.s Fri Oct 11 07:53:26 2019
@@ -35,10 +35,10 @@ ds_read_u16_d16 v5, v1
ds_read_u16_d16_hi v5, v1
// GFX6-8: error: instruction not supported on this GPU
-ds_write_addtid_b32 v5, v1
+ds_write_addtid_b32 v5
// GFX6-8: error: instruction not supported on this GPU
-ds_read_addtid_b32 v5, v1
+ds_read_addtid_b32 v5
// GFX6-8: error: instruction not supported on this GPU
// GFX8+.
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt?rev=374561&r1=374560&r2=374561&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt Fri Oct 11 07:53:26 2019
@@ -5762,23 +5762,23 @@
# GFX10: ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05]
0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05
-# GFX10: ds_read_addtid_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0xff]
-0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0xff
+# GFX10: ds_read_addtid_b32 v255 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0xff]
+0xff 0xff 0xc4 0xda 0x00 0x00 0x00 0xff
-# GFX10: ds_read_addtid_b32 v5, v1 ; encoding: [0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05]
-0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05
+# GFX10: ds_read_addtid_b32 v5 ; encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
+0x00 0x00 0xc4 0xda 0x00 0x00 0x00 0x05
-# GFX10: ds_read_addtid_b32 v5, v1 offset:4 ; encoding: [0x04,0x00,0xc4,0xda,0x01,0x00,0x00,0x05]
-0x04,0x00,0xc4,0xda,0x01,0x00,0x00,0x05
+# GFX10: ds_read_addtid_b32 v5 offset:4 ; encoding: [0x04,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
+0x04 0x00 0xc4 0xda 0x00 0x00 0x00 0x05
-# GFX10: ds_read_addtid_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0x05]
-0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0x05
+# GFX10: ds_read_addtid_b32 v5 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
+0xff 0xff 0xc4 0xda 0x00 0x00 0x00 0x05
-# GFX10: ds_read_addtid_b32 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0xc6,0xda,0x01,0x00,0x00,0x05]
-0xff,0xff,0xc6,0xda,0x01,0x00,0x00,0x05
+# GFX10: ds_read_addtid_b32 v5 offset:65535 gds ; encoding: [0xff,0xff,0xc6,0xda,0x00,0x00,0x00,0x05]
+0xff 0xff 0xc6 0xda 0x00 0x00 0x00 0x05
-# GFX10: ds_read_addtid_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0xff,0x00,0x00,0x05]
-0xff,0xff,0xc4,0xda,0xff,0x00,0x00,0x05
+# GFX10: ds_read_addtid_b32 v5 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
+0xff 0xff 0xc4 0xda 0x00 0x00 0x00 0x05
# GFX10: ds_read_b128 v[252:255], v1 offset:65535 ; encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc]
0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc
@@ -7070,23 +7070,23 @@
# GFX10: ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00]
0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00
-# GFX10: ds_write_addtid_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0xff,0x01,0x00,0x00]
-0xff,0xff,0xc0,0xda,0xff,0x01,0x00,0x00
+# GFX10: ds_write_addtid_b32 v255 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x00,0xff,0x00,0x00]
+0xff 0xff 0xc0 0xda 0x00 0xff 0x00 0x00
-# GFX10: ds_write_addtid_b32 v5, v1 ; encoding: [0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00]
-0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00
+# GFX10: ds_write_addtid_b32 v5 ; encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
+0x00 0x00 0xc0 0xda 0x00 0x05 0x00 0x00
-# GFX10: ds_write_addtid_b32 v5, v1 offset:4 ; encoding: [0x04,0x00,0xc0,0xda,0x05,0x01,0x00,0x00]
-0x04,0x00,0xc0,0xda,0x05,0x01,0x00,0x00
+# GFX10: ds_write_addtid_b32 v5 offset:4 ; encoding: [0x04,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
+0x04 0x00 0xc0 0xda 0x00 0x05 0x00 0x00
-# GFX10: ds_write_addtid_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x05,0x01,0x00,0x00]
-0xff,0xff,0xc0,0xda,0x05,0x01,0x00,0x00
+# GFX10: ds_write_addtid_b32 v5 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
+0xff 0xff 0xc0 0xda 0x00 0x05 0x00 0x00
-# GFX10: ds_write_addtid_b32 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0xc2,0xda,0x05,0x01,0x00,0x00]
-0xff,0xff,0xc2,0xda,0x05,0x01,0x00,0x00
+# GFX10: ds_write_addtid_b32 v5 offset:65535 gds ; encoding: [0xff,0xff,0xc2,0xda,0x00,0x05,0x00,0x00]
+0xff 0xff 0xc2 0xda 0x00 0x05 0x00 0x00
-# GFX10: ds_write_addtid_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x05,0xff,0x00,0x00]
-0xff,0xff,0xc0,0xda,0x05,0xff,0x00,0x00
+# GFX10: ds_write_addtid_b32 v5 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
+0xff 0xff 0xc0 0xda 0x00 0x05 0x00 0x00
# GFX10: ds_write_b128 v1, v[252:255] offset:65535 ; encoding: [0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00]
0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00
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