[PATCH] D68867: [MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: atanasyan, petarj.
Herald added subscribers: llvm-commits, jrtc27, arichardson, rovka, sdardis.
Herald added a project: LLVM.

Add vector MSA register classes to fprb, they are 128 bit wide.
MSA instructions use the same registers for both integer and floating
point operations. Therefore we only need to check for vector element
size during legalization or instruction selection.

Add helper function in MipsLegalizerInfo and switch to legalIf
LegalizeRuleSet to keep legalization rules compact since they depend
on MipsSubtarget and presence of MSA.
fprb is assigned to all vector operands.
Move selectLoadStoreOpCode to MipsInstructionSelector in order to
reduce number of arguments.


Repository:
  rL LLVM

https://reviews.llvm.org/D68867

Files:
  lib/Target/Mips/MipsInstructionSelector.cpp
  lib/Target/Mips/MipsLegalizerInfo.cpp
  lib/Target/Mips/MipsRegisterBankInfo.cpp
  lib/Target/Mips/MipsRegisterBanks.td
  test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
  test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
  test/CodeGen/Mips/GlobalISel/llvm-ir/load_store_vec.ll
  test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir

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