[llvm] r374524 - [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel

[QingShan Zhang via llvm-commits]

Author: qshanz
Date: Fri Oct 11 01:36:54 2019
New Revision: 374524

URL: http://llvm.org/viewvc/llvm-project?rev=374524&view=rev
Log:
[TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel

Assume that, ModelA has scheduling resource for InstA and ModelB has scheduling resource for InstB. This is what the llvm::MCSchedClassDesc looks like:

llvm::MCSchedClassDesc ModelASchedClasses[] = {
...
InstA, 0, ...
InstB, -1,...
};

llvm::MCSchedClassDesc ModelBSchedClasses[] = {
...
InstA, -1,...
InstB, 0,...
};
The -1 means invalid num of macro ops, while it is valid if it is >=0. This is what we look like now:

llvm::MCSchedClassDesc ModelASchedClasses[] = {
...
InstA, 0, ...
InstB, 0,...
};

llvm::MCSchedClassDesc ModelBSchedClasses[] = {
...
InstA, 0,...
InstB, 0,...
};
And compiler hit the assertion here because the SCDesc is valid now for both InstA and InstB.

Differential Revision: https://reviews.llvm.org/D67950


Added:
    llvm/trunk/test/TableGen/InvalidMCSchedClassDesc.td
Modified:
    llvm/trunk/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
    llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

Modified: llvm/trunk/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll?rev=374524&r1=374523&r2=374524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll Fri Oct 11 01:36:54 2019
@@ -45,7 +45,6 @@ entry:
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
-; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: bne .LBB0_1
 
 for.body:

Added: llvm/trunk/test/TableGen/InvalidMCSchedClassDesc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/InvalidMCSchedClassDesc.td?rev=374524&view=auto
==============================================================================
--- llvm/trunk/test/TableGen/InvalidMCSchedClassDesc.td (added)
+++ llvm/trunk/test/TableGen/InvalidMCSchedClassDesc.td Fri Oct 11 01:36:54 2019
@@ -0,0 +1,47 @@
+// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
+// Check if it is valid MCSchedClassDesc if didn't have the resources. 
+
+include "llvm/Target/Target.td"
+
+def MyTarget : Target;
+
+let OutOperandList = (outs), InOperandList = (ins) in {
+  def Inst_A : Instruction; 
+  def Inst_B : Instruction; 
+}
+
+let CompleteModel = 0 in {
+  def SchedModel_A: SchedMachineModel;
+  def SchedModel_B: SchedMachineModel;
+  def SchedModel_C: SchedMachineModel;
+}
+
+// Inst_B didn't have the resoures, and it is invalid.
+// CHECK: SchedModel_ASchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             1
+// CHECK-NEXT: {DBGFIELD("Inst_B")             16383 
+let SchedModel = SchedModel_A in {
+  def Write_A : SchedWriteRes<[]>;
+  def : InstRW<[Write_A], (instrs Inst_A)>;
+}
+
+// Inst_A didn't have the resoures, and it is invalid.
+// CHECK: SchedModel_BSchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             16383 
+// CHECK-NEXT: {DBGFIELD("Inst_B")             1 
+let SchedModel = SchedModel_B in {
+  def Write_B: SchedWriteRes<[]>; 
+  def : InstRW<[Write_B], (instrs Inst_B)>;
+}
+
+// CHECK: SchedModel_CSchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             1
+// CHECK-NEXT: {DBGFIELD("Inst_B")             1
+let SchedModel = SchedModel_C in {
+  def Write_C: SchedWriteRes<[]>; 
+  def : InstRW<[Write_C], (instrs Inst_A, Inst_B)>;
+}
+
+def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
+def ProcessorB: ProcessorModel<"ProcessorB", SchedModel_B, []>;
+def ProcessorC: ProcessorModel<"ProcessorC", SchedModel_C, []>;

Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=374524&r1=374523&r2=374524&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Fri Oct 11 01:36:54 2019
@@ -1057,6 +1057,7 @@ void SubtargetEmitter::GenSchedClassTabl
         LLVM_DEBUG(dbgs() << ProcModel.ModelName
                           << " does not have resources for class " << SC.Name
                           << '\n');
+        SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
       }
     }
     // Sum resources across all operand writes.