[PATCH] D68793: [System Model] [TTI] Add TTI interfaces for write-combining buffers

[Hal Finkel via Phabricator via llvm-commits]

hfinkel added a comment.

In D68793#1704496 <https://reviews.llvm.org/D68793#1704496>, @greened wrote:

> In D68793#1704266 <https://reviews.llvm.org/D68793#1704266>, @hfinkel wrote:
>
> > How do you imagine that we'd use this? Do we need some kind of size to go along with this?
>
>
> See the Intel optimization guide, section 3.6.9.
>
> https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf
>
> Basically, this information can be used to inform loop transformations as well as use of non-temporal instructions.  A write-combining buffer is not the same as a store buffer.  A write-combining buffer is always one cache line in size, so I don't think we need size information.


Alright, thanks. First, we should document this in the interface. Instead of just saying:

  \return the number of write-combining buffers.

we might say something like:

  \return the number of write-combining buffers. A write-combining buffer is a per-core resource used for collecting writes to a particular cache line before further processing those writes using other parts of the memory subsystem.

we already have getCacheLineSize(), so we know how big that is, but we don't currently have a way to account for how many hardware threads per core, right? Don't we need that to estimate how many write-combining buffers we get for the current hardware thread? (Presumably, we'd want the same thing to use the total-cache-size functions too, because we need to generate code assuming a working-set size per thread?)

The Intel optimization guide talks about using this number to drive loop distribution, where we don't update more arrays (cache lines) at a time than can fit into the thread's WC buffers. Is this what you had in mind?


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