[PATCH] D68821: AMDGPU: Relax 32-bit SGPR register class
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 10 11:31:26 PDT 2019
arsenm created this revision.
arsenm added reviewers: rampitec, kerbowa, nhaehnle.
Herald added subscribers: arphaman, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl.
Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This
will allow the register coalescer to do a better job eliminating
copies to m0.
For GlobalISel, as a terrible hack, use SGPR_32 for things that should
use SCC until booleans are solved.
https://reviews.llvm.org/D68821
Files:
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SIRegisterInfo.cpp
lib/Target/AMDGPU/SIRegisterInfo.h
test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
test/CodeGen/AMDGPU/inline-constraints.ll
test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
test/CodeGen/AMDGPU/read_register.ll
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