[PATCH] D68632: [X86] Make memcmp() use PTEST if possible and also enable AVX1

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

This should fix the scaliarization issue seen with ISD::XOR and ISD::OR

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 377c608..92d1166 100644

- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4344,7 +4344,9 @@ SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {

  if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
       Level <= AfterLegalizeTypes) {
    // Input types must be integer and the same.

- if (XVT.isInteger() && XVT == Y.getValueType()) {

+    if (XVT.isInteger() && XVT == Y.getValueType() &&
+        !(VT.isVector() && TLI.isTypeLegal(VT) &&
+          !XVT.isVector() && !TLI.isTypeLegal(XVT))) {

    SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
    return DAG.getNode(HandOpcode, DL, VT, Logic);
  }


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68632/new/

https://reviews.llvm.org/D68632