[llvm] r374397 - [DAGCombiner] fold select-of-constants to shift

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Thu Oct 10 10:52:02 2019
New Revision: 374397

URL: http://llvm.org/viewvc/llvm-project?rev=374397&view=rev
Log:
[DAGCombiner] fold select-of-constants to shift

This reverses the scalar canonicalization proposed in D63382.

Pre: isPowerOf2(C1)
%r = select i1 %cond, i32 C1, i32 0
=>
%z = zext i1 %cond to i32
%r = shl i32 %z, log2(C1)

https://rise4fun.com/Alive/Z50

x86 already tries to fold this pattern, but it isn't done
uniformly, so we still see a diff. AArch64 probably should
enable the TLI hook to benefit too, but that's a follow-on.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=374397&r1=374396&r2=374397&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Oct 10 10:52:02 2019
@@ -8221,10 +8221,11 @@ SDValue DAGCombiner::foldSelectOfConstan
       return Cond;
     }
 
-    // For any constants that differ by 1, we can transform the select into an
-    // extend and add. Use a target hook because some targets may prefer to
-    // transform in the other direction.
+    // Use a target hook because some targets may prefer to transform in the
+    // other direction.
     if (TLI.convertSelectOfConstantsToMath(VT)) {
+      // For any constants that differ by 1, we can transform the select into an
+      // extend and add.
       const APInt &C1Val = C1->getAPIntValue();
       const APInt &C2Val = C2->getAPIntValue();
       if (C1Val - 1 == C2Val) {
@@ -8239,6 +8240,14 @@ SDValue DAGCombiner::foldSelectOfConstan
           Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
         return DAG.getNode(ISD::ADD, DL, VT, Cond, N2);
       }
+
+      // select Cond, Pow2, 0 --> (zext Cond) << log2(Pow2)
+      if (C1Val.isPowerOf2() && C2Val.isNullValue()) {
+        if (VT != MVT::i1)
+          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
+        SDValue ShAmtC = DAG.getConstant(C1Val.exactLogBase2(), DL, VT);
+        return DAG.getNode(ISD::SHL, DL, VT, Cond, ShAmtC);
+      }
     }
 
     return SDValue();

Modified: llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll?rev=374397&r1=374396&r2=374397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll (original)
+++ llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll Thu Oct 10 10:52:02 2019
@@ -202,19 +202,15 @@ define i32 @PR31175(i32 %x, i32 %y) {
 define i8 @sel_shift_bool_i8(i1 %t) {
 ; CHECK-NOBMI-LABEL: sel_shift_bool_i8:
 ; CHECK-NOBMI:       # %bb.0:
-; CHECK-NOBMI-NEXT:    # kill: def $edi killed $edi def $rdi
-; CHECK-NOBMI-NEXT:    notb %dil
-; CHECK-NOBMI-NEXT:    shlb $7, %dil
-; CHECK-NOBMI-NEXT:    leal -128(%rdi), %eax
+; CHECK-NOBMI-NEXT:    movl %edi, %eax
+; CHECK-NOBMI-NEXT:    shlb $7, %al
 ; CHECK-NOBMI-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-NOBMI-NEXT:    retq
 ;
 ; CHECK-BMI-LABEL: sel_shift_bool_i8:
 ; CHECK-BMI:       # %bb.0:
-; CHECK-BMI-NEXT:    # kill: def $edi killed $edi def $rdi
-; CHECK-BMI-NEXT:    notb %dil
-; CHECK-BMI-NEXT:    shlb $7, %dil
-; CHECK-BMI-NEXT:    leal -128(%rdi), %eax
+; CHECK-BMI-NEXT:    movl %edi, %eax
+; CHECK-BMI-NEXT:    shlb $7, %al
 ; CHECK-BMI-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-BMI-NEXT:    retq
   %shl = select i1 %t, i8 128, i8 0